[llvm] 1778d68 - Revert "[AArch64][GlobalISel] Adopt dup(load) -> LD1R patterns from SelectionDAG"
David Spickett via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 21 05:33:28 PDT 2023
Author: David Spickett
Date: 2023-09-21T12:33:11Z
New Revision: 1778d6802beff204a532e238c7186b3e08926004
URL: https://github.com/llvm/llvm-project/commit/1778d6802beff204a532e238c7186b3e08926004
DIFF: https://github.com/llvm/llvm-project/commit/1778d6802beff204a532e238c7186b3e08926004.diff
LOG: Revert "[AArch64][GlobalISel] Adopt dup(load) -> LD1R patterns from SelectionDAG"
This reverts commit fb8f59156f0f208f6192ed808fc223eda6c0e7ec and
b8e9450acb1ad10d002a85b7dafa9d14c764478f.
Due to test suite failures on AArch64:
https://lab.llvm.org/buildbot/#/builders/183/builds/16057
Added:
Modified:
llvm/lib/Target/AArch64/AArch64InstrGISel.td
llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
llvm/test/CodeGen/AArch64/arm64-ld1.ll
llvm/test/CodeGen/AArch64/arm64-st1.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrGISel.td b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
index b47605c0b797cf8..0f3ef2327769eae 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrGISel.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrGISel.td
@@ -496,20 +496,3 @@ let AddedComplexity = 19 in {
defm : VecROStoreLane64_0Pat<ro16, store, v4i16, i16, hsub, STRHroW, STRHroX>;
defm : VecROStoreLane64_0Pat<ro32, store, v2i32, i32, ssub, STRSroW, STRSroX>;
}
-
-def : Pat<(v8i8 (AArch64dup (i8 (load (am_indexed8 GPR64sp:$Rn))))),
- (LD1Rv8b GPR64sp:$Rn)>;
-def : Pat<(v16i8 (AArch64dup (i8 (load GPR64sp:$Rn)))),
- (LD1Rv16b GPR64sp:$Rn)>;
-def : Pat<(v4i16 (AArch64dup (i16 (load GPR64sp:$Rn)))),
- (LD1Rv4h GPR64sp:$Rn)>;
-def : Pat<(v8i16 (AArch64dup (i16 (load GPR64sp:$Rn)))),
- (LD1Rv8h GPR64sp:$Rn)>;
-def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
- (LD1Rv2s GPR64sp:$Rn)>;
-def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
- (LD1Rv4s GPR64sp:$Rn)>;
-def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
- (LD1Rv2d GPR64sp:$Rn)>;
-def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
- (LD1Rv1d GPR64sp:$Rn)>;
diff --git a/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll b/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
index 53cc5ce86373fb2..6657b19d24929d8 100644
--- a/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm64-apple-ios7.0 -o - %s | FileCheck %s --check-prefix=CHECK
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=arm64-apple-ios7.0 -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-GISEL
+; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=arm64-apple-ios7.0 -o - %s | FileCheck %s --check-prefix=CHECK-GISEL
; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_pre_load
; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_load
@@ -620,6 +620,9 @@
; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_i8
; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_i16
; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_i32
+; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_v3i32_small_align
+; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_v3i32_default_align
+; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_valid_const_index_v3i32
; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_masked_i32
; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_masked2_i32
@@ -13791,9 +13794,8 @@ define <16 x i8> @test_v16i8_post_imm_ld1r(ptr %bar, ptr %ptr) {
;
; CHECK-GISEL-LABEL: test_v16i8_post_imm_ld1r:
; CHECK-GISEL: ; %bb.0:
-; CHECK-GISEL-NEXT: ld1r.16b { v0 }, [x0]
-; CHECK-GISEL-NEXT: add x8, x0, #1
-; CHECK-GISEL-NEXT: str x8, [x1]
+; CHECK-GISEL-NEXT: ld1r.16b { v0 }, [x0], #1
+; CHECK-GISEL-NEXT: str x0, [x1]
; CHECK-GISEL-NEXT: ret
%tmp1 = load i8, ptr %bar
%tmp2 = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
@@ -13826,9 +13828,8 @@ define <16 x i8> @test_v16i8_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) {
;
; CHECK-GISEL-LABEL: test_v16i8_post_reg_ld1r:
; CHECK-GISEL: ; %bb.0:
-; CHECK-GISEL-NEXT: ld1r.16b { v0 }, [x0]
-; CHECK-GISEL-NEXT: add x8, x0, x2
-; CHECK-GISEL-NEXT: str x8, [x1]
+; CHECK-GISEL-NEXT: ld1r.16b { v0 }, [x0], x2
+; CHECK-GISEL-NEXT: str x0, [x1]
; CHECK-GISEL-NEXT: ret
%tmp1 = load i8, ptr %bar
%tmp2 = insertelement <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
@@ -13861,9 +13862,8 @@ define <8 x i8> @test_v8i8_post_imm_ld1r(ptr %bar, ptr %ptr) {
;
; CHECK-GISEL-LABEL: test_v8i8_post_imm_ld1r:
; CHECK-GISEL: ; %bb.0:
-; CHECK-GISEL-NEXT: ld1r.8b { v0 }, [x0]
-; CHECK-GISEL-NEXT: add x8, x0, #1
-; CHECK-GISEL-NEXT: str x8, [x1]
+; CHECK-GISEL-NEXT: ld1r.8b { v0 }, [x0], #1
+; CHECK-GISEL-NEXT: str x0, [x1]
; CHECK-GISEL-NEXT: ret
%tmp1 = load i8, ptr %bar
%tmp2 = insertelement <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
@@ -13888,9 +13888,8 @@ define <8 x i8> @test_v8i8_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) {
;
; CHECK-GISEL-LABEL: test_v8i8_post_reg_ld1r:
; CHECK-GISEL: ; %bb.0:
-; CHECK-GISEL-NEXT: ld1r.8b { v0 }, [x0]
-; CHECK-GISEL-NEXT: add x8, x0, x2
-; CHECK-GISEL-NEXT: str x8, [x1]
+; CHECK-GISEL-NEXT: ld1r.8b { v0 }, [x0], x2
+; CHECK-GISEL-NEXT: str x0, [x1]
; CHECK-GISEL-NEXT: ret
%tmp1 = load i8, ptr %bar
%tmp2 = insertelement <8 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 %tmp1, i32 0
diff --git a/llvm/test/CodeGen/AArch64/arm64-ld1.ll b/llvm/test/CodeGen/AArch64/arm64-ld1.ll
index 5b5ced1097e4418..96468b2cfa8ace8 100644
--- a/llvm/test/CodeGen/AArch64/arm64-ld1.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-ld1.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc < %s -global-isel=1 -global-isel-abort=1 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc < %s -global-isel=1 -global-isel-abort=2 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-GI
%struct.__neon_int8x8x2_t = type { <8 x i8>, <8 x i8> }
%struct.__neon_int8x8x3_t = type { <8 x i8>, <8 x i8>, <8 x i8> }
diff --git a/llvm/test/CodeGen/AArch64/arm64-st1.ll b/llvm/test/CodeGen/AArch64/arm64-st1.ll
index 6f87c66c873451a..121ca69bee21dd6 100644
--- a/llvm/test/CodeGen/AArch64/arm64-st1.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-st1.ll
@@ -1,5 +1,5 @@
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
-; RUN: llc < %s -global-isel -global-isel-abort=1 -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -global-isel -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
; The instruction latencies of Exynos-M3 trigger the transform we see under the Exynos check.
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs -mcpu=exynos-m3 | FileCheck --check-prefix=EXYNOS %s
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