[llvm] 0fe905d - [IndVars] Add test for #66986 (NFC)

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2023-09-21T12:47:42+02:00
New Revision: 0fe905daf0ed5a50413d0b2a231ec6b6097e7d38

URL: https://github.com/llvm/llvm-project/commit/0fe905daf0ed5a50413d0b2a231ec6b6097e7d38
DIFF: https://github.com/llvm/llvm-project/commit/0fe905daf0ed5a50413d0b2a231ec6b6097e7d38.diff

LOG: [IndVars] Add test for #66986 (NFC)

Added: 
    llvm/test/Transforms/IndVarSimplify/pr66986.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/IndVarSimplify/pr66986.ll b/llvm/test/Transforms/IndVarSimplify/pr66986.ll
new file mode 100644
index 000000000000000..f70c9d2be97df34
--- /dev/null
+++ b/llvm/test/Transforms/IndVarSimplify/pr66986.ll
@@ -0,0 +1,54 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
+; RUN: opt -S -passes=indvars < %s | FileCheck %s
+
+target datalayout = "n8:16:32:64"
+
+; FIXME: This is a miscompile.
+; The udiv should not get hoisted into the preheader (past a conditional).
+define i32 @test(i1 %c, i32 %arg1, i32 %arg2) {
+; CHECK-LABEL: define i32 @test(
+; CHECK-SAME: i1 [[C:%.*]], i32 [[ARG1:%.*]], i32 [[ARG2:%.*]]) {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = udiv i32 [[ARG1]], [[ARG2]]
+; CHECK-NEXT:    br label [[LOOP:%.*]]
+; CHECK:       loop:
+; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i32 [ [[INDVARS_IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ], [ [[TMP0]], [[ENTRY:%.*]] ]
+; CHECK-NEXT:    br i1 [[C]], label [[IF:%.*]], label [[LOOP_LATCH]]
+; CHECK:       if:
+; CHECK-NEXT:    br label [[LOOP2:%.*]]
+; CHECK:       loop2:
+; CHECK-NEXT:    [[PHI6:%.*]] = phi i64 [ [[ADD7:%.*]], [[LOOP2]] ], [ 0, [[IF]] ]
+; CHECK-NEXT:    [[ADD7]] = add nuw nsw i64 [[PHI6]], 1
+; CHECK-NEXT:    [[TMP1:%.*]] = zext i32 [[INDVARS_IV]] to i64
+; CHECK-NEXT:    [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
+; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp ne i64 [[ADD7]], [[TMP2]]
+; CHECK-NEXT:    br i1 [[EXITCOND]], label [[LOOP2]], label [[LOOP_LATCH_LOOPEXIT:%.*]]
+; CHECK:       loop.latch.loopexit:
+; CHECK-NEXT:    br label [[LOOP_LATCH]]
+; CHECK:       loop.latch:
+; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add i32 [[INDVARS_IV]], 1
+; CHECK-NEXT:    br label [[LOOP]]
+;
+entry:
+  br label %loop
+
+loop:
+  %phi = phi i32 [ %add9, %loop.latch ], [ 0, %entry ]
+  br i1 %c, label %if, label %loop.latch
+
+if:
+  %udiv = udiv i32 %arg1, %arg2
+  %add = add i32 %udiv, %phi
+  %zext = zext i32 %add to i64
+  br label %loop2
+
+loop2:
+  %phi6 = phi i64 [ %add7, %loop2 ], [ 0, %if ]
+  %add7 = add i64 %phi6, 1
+  %icmp = icmp slt i64 %phi6, %zext
+  br i1 %icmp, label %loop2, label %loop.latch
+
+loop.latch:
+  %add9 = add i32 %phi, 1
+  br label %loop
+}