[PATCH] D159533: [DAG] getNode() - fold (zext (trunc x)) -> x iff the upper bits are known zero - add SRL support

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:5698
+        if ((OpOp.getOpcode() == ISD::AssertZext && N1->hasOneUse()) ||
+            OpOp.getOpcode() == ISD::SRL) {
           APInt HiBits = APInt::getBitsSetFrom(VT.getScalarSizeInBits(),
----------------
goldstein.w.n wrote:
> Why does the `ISD::AssertZext` need one use check?
> 
> But while you're at it think `ISD::AND` also work here right?
Everything should work here - eventually the getOpcode() filters will go entirely - the problem we're having is a number of AArch64 mul folds create various zext(trunc()) patterns and then expect them to still exist later in the combine.

As usual with LLVM it comes down to yak shaving :) 


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D159533/new/

https://reviews.llvm.org/D159533