[llvm] 7cd01af - [RISCV][GISel] Add test showing missed opportunity to use X0 for the LHS of sub for negate.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-09-22T17:04:11-07:00
New Revision: 7cd01afb73a2b88ab410404932ebdaf04becd883

URL: https://github.com/llvm/llvm-project/commit/7cd01afb73a2b88ab410404932ebdaf04becd883
DIFF: https://github.com/llvm/llvm-project/commit/7cd01afb73a2b88ab410404932ebdaf04becd883.diff

LOG: [RISCV][GISel] Add test showing missed opportunity to use X0 for the LHS of sub for negate.

I had to disable the late copy propagation pass that can see through
the ADDI we were previously emitting. We really want to get this
in the register coalescer if not even earlier.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
index 4fe1691714bb958..be25efdc78d255d 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
@@ -1,8 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m -global-isel -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s --check-prefix=RV32IM
+; RUN:   -riscv-enable-copy-propagation=false | FileCheck %s --check-prefix=RV32IM
 ; RUN: llc -mtriple=riscv64 -mattr=+m -global-isel -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s --check-prefix=RV64IM
+; RUN:   -riscv-enable-copy-propagation=false | FileCheck %s --check-prefix=RV64IM
 
 ; Extends to 32 bits exhaustively tested for add only.
 
@@ -130,6 +130,23 @@ entry:
   ret i32 %0
 }
 
+define i32 @neg_i32(i32 %a) {
+; RV32IM-LABEL: neg_i32:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    li a1, 0
+; RV32IM-NEXT:    sub a0, a1, a0
+; RV32IM-NEXT:    ret
+;
+; RV64IM-LABEL: neg_i32:
+; RV64IM:       # %bb.0: # %entry
+; RV64IM-NEXT:    li a1, 0
+; RV64IM-NEXT:    subw a0, a1, a0
+; RV64IM-NEXT:    ret
+entry:
+  %0 = sub i32 0, %a
+  ret i32 %0
+}
+
 define i32 @sll_i32(i32 %a, i32 %b) {
 ; RV32IM-LABEL: sll_i32:
 ; RV32IM:       # %bb.0: # %entry
@@ -461,6 +478,27 @@ entry:
   ret i64 %0
 }
 
+define i64 @neg_i64(i64 %a) {
+; RV32IM-LABEL: neg_i64:
+; RV32IM:       # %bb.0: # %entry
+; RV32IM-NEXT:    li a3, 0
+; RV32IM-NEXT:    sub a2, a3, a0
+; RV32IM-NEXT:    sltu a0, a3, a0
+; RV32IM-NEXT:    sub a1, a3, a1
+; RV32IM-NEXT:    sub a1, a1, a0
+; RV32IM-NEXT:    mv a0, a2
+; RV32IM-NEXT:    ret
+;
+; RV64IM-LABEL: neg_i64:
+; RV64IM:       # %bb.0: # %entry
+; RV64IM-NEXT:    li a1, 0
+; RV64IM-NEXT:    sub a0, a1, a0
+; RV64IM-NEXT:    ret
+entry:
+  %0 = sub i64 0, %a
+  ret i64 %0
+}
+
 ; TODO: Handle G_SELECT, which is needed to have i64 shifts working on RV32.
 
 define i64 @and_i64(i64 %a, i64 %b) {