[llvm] [RISCV] Add searchable table for tune information (PR #66193)

[Wang Pengcheng via llvm-commits]

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@@ -2,8 +2,6 @@
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 ; RUN: llc -mtriple=riscv32 -mattr=+c -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32C
-; RUN: llc -mtriple=riscv32 -mattr=+pref-func-align-32 -verify-machineinstrs < %s \
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wangpc-pp wrote:

I found some descriptions in https://starfivetech.com/uploads/u74mc_core_complex_manual_21G1.pdf:
> 3.2.6 Instruction Fetch Unit
> The S7 instruction fetch unit is responsible for keeping the pipeline fed with instructions from
memory. The instruction fetch unit delivers up to 8 bytes of instructions per clock cycle to sup-
port superscalar instruction execution. _Fetches are always **word-aligned** and there is a one-
cycle penalty for branching to a 32-bit instruction that is not word-aligned._

It seems we'd better to align functions and hot loops to 4-byte to get best performance. But `C` extension is supported so the alignment would be 2-byte.
```
  // Function alignments.
  const Align FunctionAlignment(Subtarget.hasStdExtCOrZca() ? 2 : 4);
  setMinFunctionAlignment(FunctionAlignment);
  // Set preferred alignments.
  setPrefFunctionAlignment(Subtarget.getPrefFunctionAlignment());
  setPrefLoopAlignment(Subtarget.getPrefLoopAlignment());
```

https://github.com/llvm/llvm-project/pull/66193