[llvm] [X86] Add missed type extension when combining load for ptr32 (PR #67168)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-x86

<details>
<summary>Changes</summary>

Closes #<!-- -->66873

---
Full diff: https://github.com/llvm/llvm-project/pull/67168.diff


3 Files Affected:

- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+3-3) 
- (modified) llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll (+13) 
- (modified) llvm/test/CodeGen/X86/mixed-ptr-sizes.ll (+20) 


``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 81aa998d33c639b..484f39aaff722b6 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -49796,9 +49796,9 @@ static SDValue combineLoad(SDNode *N, SelectionDAG &DAG,
     if (PtrVT != Ld->getBasePtr().getSimpleValueType()) {
       SDValue Cast =
           DAG.getAddrSpaceCast(dl, PtrVT, Ld->getBasePtr(), AddrSpace, 0);
-      return DAG.getLoad(RegVT, dl, Ld->getChain(), Cast, Ld->getPointerInfo(),
-                         Ld->getOriginalAlign(),
-                         Ld->getMemOperand()->getFlags());
+      return DAG.getExtLoad(Ext, dl, RegVT, Ld->getChain(), Cast,
+                            Ld->getPointerInfo(), MemVT, Ld->getOriginalAlign(),
+                            Ld->getMemOperand()->getFlags());
     }
   }
 
diff --git a/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll b/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll
index 0817211f50937ed..fe41f76bfb16515 100644
--- a/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll
+++ b/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll
@@ -341,3 +341,16 @@ entry:
   store i32 %i, ptr addrspace(272) %s, align 8
   ret void
 }
+
+define i64 @test_load_sptr32_zext_i64(ptr addrspace(270) %i) {
+; ALL-LABEL: test_load_sptr32_zext_i64:
+; ALL:       # %bb.0: # %entry
+; ALL-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; ALL-NEXT:    movl (%eax), %eax
+; ALL-NEXT:    xorl %edx, %edx
+; ALL-NEXT:    retl
+entry:
+  %0 = load i32, ptr addrspace(270) %i, align 4
+  %1 = zext i32 %0 to i64
+  ret i64 %1
+}
diff --git a/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll b/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
index e88a494908701d8..56223bbb28aeac9 100644
--- a/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
+++ b/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
@@ -256,3 +256,23 @@ entry:
   store i32 %i, ptr addrspace(272) %s, align 8
   ret void
 }
+
+define i64 @test_load_sptr32_zext_i64(ptr addrspace(270) %i) {
+; CHECK-LABEL: test_load_sptr32_zext_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movslq %ecx, %rax
+; CHECK-NEXT:    movl (%rax), %eax
+; CHECK-NEXT:    retq
+;
+; CHECK-O0-LABEL: test_load_sptr32_zext_i64:
+; CHECK-O0:       # %bb.0: # %entry
+; CHECK-O0-NEXT:    movslq %ecx, %rax
+; CHECK-O0-NEXT:    movl (%rax), %eax
+; CHECK-O0-NEXT:    movl %eax, %eax
+; CHECK-O0-NEXT:    # kill: def $rax killed $eax
+; CHECK-O0-NEXT:    retq
+entry:
+  %0 = load i32, ptr addrspace(270) %i, align 4
+  %1 = zext i32 %0 to i64
+  ret i64 %1
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/67168