[llvm] 2aff14e - [gn build] Manually port 8e87dc10

[Arthur Eubanks via llvm-commits]

Author: Arthur Eubanks
Date: 2023-09-22T12:22:35-07:00
New Revision: 2aff14ef3e41ef0e2290dd33f321f06e51da8364

URL: https://github.com/llvm/llvm-project/commit/2aff14ef3e41ef0e2290dd33f321f06e51da8364
DIFF: https://github.com/llvm/llvm-project/commit/2aff14ef3e41ef0e2290dd33f321f06e51da8364.diff

LOG: [gn build] Manually port 8e87dc10

Added: 
    

Modified: 
    llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn

Removed: 
    


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diff  --git a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
index d13c07b36c96822..0fa65102071615d 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
@@ -50,6 +50,15 @@ tablegen("RISCVGenPreLegalizeGICombiner") {
   td_file = "RISCVGISel.td"
 }
 
+tablegen("RISCVGenPostLegalizeGICombiner") {
+  visibility = [ ":LLVMRISCVCodeGen" ]
+  args = [
+    "-gen-global-isel-combiner",
+    "-combiners=RISCVPostLegalizerCombiner",
+  ]
+  td_file = "RISCVGISel.td"
+}
+
 tablegen("RISCVGenRegisterBank") {
   visibility = [ ":LLVMRISCVCodeGen" ]
   args = [ "-gen-register-bank" ]
@@ -63,6 +72,7 @@ static_library("LLVMRISCVCodeGen") {
     ":RISCVGenGlobalISel",
     ":RISCVGenMCPseudoLowering",
     ":RISCVGenO0PreLegalizeGICombiner",
+    ":RISCVGenPostLegalizeGICombiner",
     ":RISCVGenPreLegalizeGICombiner",
     ":RISCVGenRegisterBank",
 
@@ -88,6 +98,7 @@ static_library("LLVMRISCVCodeGen") {
     "GISel/RISCVInstructionSelector.cpp",
     "GISel/RISCVLegalizerInfo.cpp",
     "GISel/RISCVO0PreLegalizerCombiner.cpp",
+    "GISel/RISCVPostLegalizerCombiner.cpp",
     "GISel/RISCVPreLegalizerCombiner.cpp",
     "GISel/RISCVRegisterBankInfo.cpp",
     "RISCVAsmPrinter.cpp",