[PATCH] D159533: [DAG] getNode() - fold (zext (trunc x)) -> x iff the upper bits are known zero - add SRL support

[Jeffrey Byrnes via Phabricator via llvm-commits]

jrbyrnes added a comment.

In D159533#4649035 <https://reviews.llvm.org/D159533#4649035>, @RKSimon wrote:

> @jrbyrnes I've pulled the AMDGPUISD::PERM matching out of performOrCombine, made it into a 'matchPERM' helper and setup ISD::FSHR to use it - is this what you had in mind?

Yes something along these lines, although we will need to teach calculateByteProvider about ISD::FSHR (and might as well teach about ISD::FSHL) -- I'm working on this patch currently.


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