[llvm] [RISCV] Use LMUL=1 for vmv_s_x_vl with non-undef passthru (PR #66659)

[Philip Reames via llvm-commits]

================
@@ -550,9 +550,9 @@ define void @insertelt_c6_v8i64_0_add(ptr %x, ptr %y) {
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    li a2, 6
-; CHECK-NEXT:    vsetvli zero, zero, e64, m4, tu, ma
+; CHECK-NEXT:    vsetivli zero, 8, e64, m1, tu, ma
----------------
preames wrote:

I think there's a legality issue here.  Since the vmv.s.x has a register class which only requires m1, it could chose an unaligned (for m4) register.  This would result in an illegal instruction if we allow the m4 to forward over the m1 vmv.s.x.  We'd have to change the register class constraints to do this legally. 

https://github.com/llvm/llvm-project/pull/66659