[PATCH] D151848: [X86, Peephole] Enable FoldImmediate for X86

[Guozhi Wei via Phabricator via llvm-commits]

Carrot updated this revision to Diff 557127.
Carrot marked 6 inline comments as done.
Carrot added a comment.

Thanks for the suggestion for more test cases. It did reveals two missed opportunities in Peephole pass.

1. The function PeepholeOptimizer::isMoveImmediate checks only MI.isMoveImmediate() for immediate, but on x86-64 we use the following code sequence to setup 64b immediate. We can use TII->getConstValDefinedInReg to find more immediate setup instructions.

  %8:gr32 = MOV32r0 implicit-def dead $eflags
  %6:gr64 = SUBREG_TO_REG 0, killed %8:gr32, %subreg.sub_32bit



2. Peephole only tracks virtual register  contains immediate value. On x86 shift instructions use physical register $cl to specify shift amount. In order to fold immediate values into shift instructions we need to track physical register. In SSA form, tracking virtual register is very simple, but tracking physical register is more complex, it also consumes more compile time. So I didn't enhance it here. But FoldImmediate for shift instructions are still useful for D119916 <https://reviews.llvm.org/D119916>, and will be tested in https://reviews.llvm.org/D119916#change-nKHV7D4KKS4t.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151848/new/

https://reviews.llvm.org/D151848

Files:
  llvm/lib/CodeGen/PeepholeOptimizer.cpp
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrInfo.h
  llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir
  llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
  llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
  llvm/test/CodeGen/X86/fast-isel-freeze.ll
  llvm/test/CodeGen/X86/foldimmediate-size.ll
  llvm/test/CodeGen/X86/foldimmediate.mir
  llvm/test/CodeGen/X86/pcsections-atomics.ll
  llvm/test/CodeGen/X86/physreg-pairs.ll
  llvm/test/CodeGen/X86/popcnt.ll
  llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
  llvm/test/CodeGen/X86/remat-phys-dead.ll
  llvm/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll
  llvm/test/CodeGen/X86/swifterror.ll
  llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll

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