[llvm] 976df42 - [RISCV] Fix bugs about register list of Zcmp push/pop. (#66073)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 20 00:20:18 PDT 2023
Author: Yeting Kuo
Date: 2023-09-20T15:20:13+08:00
New Revision: 976df42e6af5bcbd906e1bc0dc62a1aaf23a360d
URL: https://github.com/llvm/llvm-project/commit/976df42e6af5bcbd906e1bc0dc62a1aaf23a360d
DIFF: https://github.com/llvm/llvm-project/commit/976df42e6af5bcbd906e1bc0dc62a1aaf23a360d.diff
LOG: [RISCV] Fix bugs about register list of Zcmp push/pop. (#66073)
The pr does two things. One is to fix internal compiler error when we
need to spill callee saves but none of them is GPR, another is to fix
wrong register number for pushed registers are {ra, s0-s11}.
Added:
llvm/test/CodeGen/RISCV/zcmp-with-float.ll
Modified:
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index cbcf41a979c9e47..50e98e6b8ea99a0 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -226,37 +226,38 @@ getRestoreLibCallName(const MachineFunction &MF,
return RestoreLibCalls[LibCallID];
}
-// Return encoded value for PUSH/POP instruction, representing
-// registers to store/load.
-static unsigned getPushPopEncoding(const Register MaxReg) {
+// Return encoded value and register count for PUSH/POP instruction,
+// representing registers to store/load.
+static std::pair<unsigned, unsigned>
+getPushPopEncodingAndNum(const Register MaxReg) {
switch (MaxReg) {
default:
llvm_unreachable("Unexpected Reg for Push/Pop Inst");
case RISCV::X27: /*s11*/
case RISCV::X26: /*s10*/
- return llvm::RISCVZC::RLISTENCODE::RA_S0_S11;
+ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S11, 13);
case RISCV::X25: /*s9*/
- return llvm::RISCVZC::RLISTENCODE::RA_S0_S9;
+ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S9, 11);
case RISCV::X24: /*s8*/
- return llvm::RISCVZC::RLISTENCODE::RA_S0_S8;
+ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S8, 10);
case RISCV::X23: /*s7*/
- return llvm::RISCVZC::RLISTENCODE::RA_S0_S7;
+ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S7, 9);
case RISCV::X22: /*s6*/
- return llvm::RISCVZC::RLISTENCODE::RA_S0_S6;
+ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S6, 8);
case RISCV::X21: /*s5*/
- return llvm::RISCVZC::RLISTENCODE::RA_S0_S5;
+ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S5, 7);
case RISCV::X20: /*s4*/
- return llvm::RISCVZC::RLISTENCODE::RA_S0_S4;
+ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S4, 6);
case RISCV::X19: /*s3*/
- return llvm::RISCVZC::RLISTENCODE::RA_S0_S3;
+ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S3, 5);
case RISCV::X18: /*s2*/
- return llvm::RISCVZC::RLISTENCODE::RA_S0_S2;
+ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S2, 4);
case RISCV::X9: /*s1*/
- return llvm::RISCVZC::RLISTENCODE::RA_S0_S1;
+ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0_S1, 3);
case RISCV::X8: /*s0*/
- return llvm::RISCVZC::RLISTENCODE::RA_S0;
+ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA_S0, 2);
case RISCV::X1: /*ra*/
- return llvm::RISCVZC::RLISTENCODE::RA;
+ return std::make_pair(llvm::RISCVZC::RLISTENCODE::RA, 1);
}
}
@@ -1360,14 +1361,12 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
RISCVMachineFunctionInfo *RVFI = MF->getInfo<RISCVMachineFunctionInfo>();
if (RVFI->isPushable(*MF)) {
Register MaxReg = getMaxPushPopReg(*MF, CSI);
- unsigned PushedRegNum =
- getPushPopEncoding(MaxReg) - llvm::RISCVZC::RLISTENCODE::RA + 1;
- RVFI->setRVPushRegs(PushedRegNum);
- RVFI->setRVPushStackSize(alignTo((STI.getXLen() / 8) * PushedRegNum, 16));
-
if (MaxReg != RISCV::NoRegister) {
+ auto [RegEnc, PushedRegNum] = getPushPopEncodingAndNum(MaxReg);
+ RVFI->setRVPushRegs(PushedRegNum);
+ RVFI->setRVPushStackSize(alignTo((STI.getXLen() / 8) * PushedRegNum, 16));
+
// Use encoded number to represent registers to spill.
- unsigned RegEnc = getPushPopEncoding(MaxReg);
RVFI->setRVPushRlist(RegEnc);
MachineInstrBuilder PushBuilder =
BuildMI(MBB, MI, DL, TII.get(RISCV::CM_PUSH))
diff --git a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
index ca290988b58ca14..09ecbbc7e8feb81 100644
--- a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
+++ b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
@@ -2128,6 +2128,142 @@ entry:
ret void
}
+; Check .cfi_offset of s11 is correct for Zcmp.
+define void @bar() {
+; RV32I-LABEL: bar:
+; RV32I: # %bb.0: # %entry
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: .cfi_def_cfa_offset 16
+; RV32I-NEXT: sw s11, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: .cfi_offset s11, -4
+; RV32I-NEXT: #APP
+; RV32I-NEXT: li s11, 0
+; RV32I-NEXT: #NO_APP
+; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32I-WITH-FP-LABEL: bar:
+; RV32I-WITH-FP: # %bb.0: # %entry
+; RV32I-WITH-FP-NEXT: addi sp, sp, -16
+; RV32I-WITH-FP-NEXT: .cfi_def_cfa_offset 16
+; RV32I-WITH-FP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-WITH-FP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-WITH-FP-NEXT: sw s11, 4(sp) # 4-byte Folded Spill
+; RV32I-WITH-FP-NEXT: .cfi_offset ra, -4
+; RV32I-WITH-FP-NEXT: .cfi_offset s0, -8
+; RV32I-WITH-FP-NEXT: .cfi_offset s11, -12
+; RV32I-WITH-FP-NEXT: addi s0, sp, 16
+; RV32I-WITH-FP-NEXT: .cfi_def_cfa s0, 0
+; RV32I-WITH-FP-NEXT: #APP
+; RV32I-WITH-FP-NEXT: li s11, 0
+; RV32I-WITH-FP-NEXT: #NO_APP
+; RV32I-WITH-FP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-WITH-FP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-WITH-FP-NEXT: lw s11, 4(sp) # 4-byte Folded Reload
+; RV32I-WITH-FP-NEXT: addi sp, sp, 16
+; RV32I-WITH-FP-NEXT: ret
+;
+; RV32IZCMP-LABEL: bar:
+; RV32IZCMP: # %bb.0: # %entry
+; RV32IZCMP-NEXT: cm.push {ra, s0-s11}, -64
+; RV32IZCMP-NEXT: .cfi_def_cfa_offset 64
+; RV32IZCMP-NEXT: .cfi_offset s11, -4
+; RV32IZCMP-NEXT: #APP
+; RV32IZCMP-NEXT: li s11, 0
+; RV32IZCMP-NEXT: #NO_APP
+; RV32IZCMP-NEXT: cm.popret {ra, s0-s11}, 64
+;
+; RV32IZCMP-WITH-FP-LABEL: bar:
+; RV32IZCMP-WITH-FP: # %bb.0: # %entry
+; RV32IZCMP-WITH-FP-NEXT: addi sp, sp, -16
+; RV32IZCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 16
+; RV32IZCMP-WITH-FP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZCMP-WITH-FP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZCMP-WITH-FP-NEXT: sw s11, 4(sp) # 4-byte Folded Spill
+; RV32IZCMP-WITH-FP-NEXT: .cfi_offset ra, -4
+; RV32IZCMP-WITH-FP-NEXT: .cfi_offset s0, -8
+; RV32IZCMP-WITH-FP-NEXT: .cfi_offset s11, -12
+; RV32IZCMP-WITH-FP-NEXT: addi s0, sp, 16
+; RV32IZCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
+; RV32IZCMP-WITH-FP-NEXT: #APP
+; RV32IZCMP-WITH-FP-NEXT: li s11, 0
+; RV32IZCMP-WITH-FP-NEXT: #NO_APP
+; RV32IZCMP-WITH-FP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZCMP-WITH-FP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZCMP-WITH-FP-NEXT: lw s11, 4(sp) # 4-byte Folded Reload
+; RV32IZCMP-WITH-FP-NEXT: addi sp, sp, 16
+; RV32IZCMP-WITH-FP-NEXT: ret
+;
+; RV64I-LABEL: bar:
+; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: .cfi_def_cfa_offset 16
+; RV64I-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: .cfi_offset s11, -8
+; RV64I-NEXT: #APP
+; RV64I-NEXT: li s11, 0
+; RV64I-NEXT: #NO_APP
+; RV64I-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64I-WITH-FP-LABEL: bar:
+; RV64I-WITH-FP: # %bb.0: # %entry
+; RV64I-WITH-FP-NEXT: addi sp, sp, -32
+; RV64I-WITH-FP-NEXT: .cfi_def_cfa_offset 32
+; RV64I-WITH-FP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-WITH-FP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-WITH-FP-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
+; RV64I-WITH-FP-NEXT: .cfi_offset ra, -8
+; RV64I-WITH-FP-NEXT: .cfi_offset s0, -16
+; RV64I-WITH-FP-NEXT: .cfi_offset s11, -24
+; RV64I-WITH-FP-NEXT: addi s0, sp, 32
+; RV64I-WITH-FP-NEXT: .cfi_def_cfa s0, 0
+; RV64I-WITH-FP-NEXT: #APP
+; RV64I-WITH-FP-NEXT: li s11, 0
+; RV64I-WITH-FP-NEXT: #NO_APP
+; RV64I-WITH-FP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-WITH-FP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-WITH-FP-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
+; RV64I-WITH-FP-NEXT: addi sp, sp, 32
+; RV64I-WITH-FP-NEXT: ret
+;
+; RV64IZCMP-LABEL: bar:
+; RV64IZCMP: # %bb.0: # %entry
+; RV64IZCMP-NEXT: cm.push {ra, s0-s11}, -112
+; RV64IZCMP-NEXT: .cfi_def_cfa_offset 112
+; RV64IZCMP-NEXT: .cfi_offset s11, -8
+; RV64IZCMP-NEXT: #APP
+; RV64IZCMP-NEXT: li s11, 0
+; RV64IZCMP-NEXT: #NO_APP
+; RV64IZCMP-NEXT: cm.popret {ra, s0-s11}, 112
+;
+; RV64IZCMP-WITH-FP-LABEL: bar:
+; RV64IZCMP-WITH-FP: # %bb.0: # %entry
+; RV64IZCMP-WITH-FP-NEXT: addi sp, sp, -32
+; RV64IZCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 32
+; RV64IZCMP-WITH-FP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64IZCMP-WITH-FP-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64IZCMP-WITH-FP-NEXT: sd s11, 8(sp) # 8-byte Folded Spill
+; RV64IZCMP-WITH-FP-NEXT: .cfi_offset ra, -8
+; RV64IZCMP-WITH-FP-NEXT: .cfi_offset s0, -16
+; RV64IZCMP-WITH-FP-NEXT: .cfi_offset s11, -24
+; RV64IZCMP-WITH-FP-NEXT: addi s0, sp, 32
+; RV64IZCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
+; RV64IZCMP-WITH-FP-NEXT: #APP
+; RV64IZCMP-WITH-FP-NEXT: li s11, 0
+; RV64IZCMP-WITH-FP-NEXT: #NO_APP
+; RV64IZCMP-WITH-FP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64IZCMP-WITH-FP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64IZCMP-WITH-FP-NEXT: ld s11, 8(sp) # 8-byte Folded Reload
+; RV64IZCMP-WITH-FP-NEXT: addi sp, sp, 32
+; RV64IZCMP-WITH-FP-NEXT: ret
+entry:
+ tail call void asm sideeffect "li s11, 0", "~{s11}"()
+ ret void
+}
+
define void @varargs(...) {
; RV32I-LABEL: varargs:
; RV32I: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/zcmp-with-float.ll b/llvm/test/CodeGen/RISCV/zcmp-with-float.ll
new file mode 100644
index 000000000000000..05ee92c89db7ca2
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/zcmp-with-float.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=riscv32 -mattr=+f,+zcmp -target-abi ilp32f -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV32
+; RUN: llc -mtriple=riscv64 -mattr=+f,+zcmp -target-abi lp64f -verify-machineinstrs < %s | FileCheck %s --check-prefix=RV64
+
+declare void @callee()
+
+; Test the file could be compiled successfully.
+; .cfi_offset of fs0 is wrong here. It should be fixed by #66613.
+define float @foo(float %arg) {
+; RV32-LABEL: foo:
+; RV32: # %bb.0: # %entry
+; RV32-NEXT: cm.push {ra}, -32
+; RV32-NEXT: .cfi_def_cfa_offset 32
+; RV32-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill
+; RV32-NEXT: .cfi_offset ra, -4
+; RV32-NEXT: .cfi_offset fs0, -4
+; RV32-NEXT: fmv.s fs0, fa0
+; RV32-NEXT: call callee at plt
+; RV32-NEXT: fmv.s fa0, fs0
+; RV32-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT: cm.popret {ra}, 32
+;
+; RV64-LABEL: foo:
+; RV64: # %bb.0: # %entry
+; RV64-NEXT: cm.push {ra}, -32
+; RV64-NEXT: .cfi_def_cfa_offset 32
+; RV64-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill
+; RV64-NEXT: .cfi_offset ra, -8
+; RV64-NEXT: .cfi_offset fs0, -4
+; RV64-NEXT: fmv.s fs0, fa0
+; RV64-NEXT: call callee at plt
+; RV64-NEXT: fmv.s fa0, fs0
+; RV64-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload
+; RV64-NEXT: cm.popret {ra}, 32
+entry:
+ call void @callee()
+ ret float %arg
+}
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