[llvm] [RISCV] Improve constant materialization by using a sequence that end… (PR #66943)

[Philip Reames via llvm-commits]

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@@ -206,10 +206,25 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
   assert(ActiveFeatures[RISCV::Feature64Bit] &&
          "Expected RV32 to only need 2 instructions");
 
+  // If the lower 13 bits are something like 0x17ff, try to turn it into 0x1800
+  // and use a final addi to correct it back to 0x17ff. This will create a
+  // sequence ending in 2 addis.
+  if ((Val & 0xfff) != 0 && (Val & 0x1800) == 0x1000) {
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preames wrote:

I think I'm missing something here.  It looks like you're checking that bit 12 is clear, and that bit 13 is set.  I think I get the bit 12 being clear part - that's required for the negative offset we're creating to not cascade - but why check that bit 13 is set?

https://github.com/llvm/llvm-project/pull/66943