[PATCH] D159533: [DAG] getNode() - fold (zext (trunc x)) -> x iff the upper bits are known zero - add SRL support

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: jrbyrnes, foad, arsenm.
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This is part of the work to address the D155472 <https://reviews.llvm.org/D155472> regressions, there's a number of issues with generalizing this fold which is why I'm just adding SRL support atm.

The fold encourages the creation of ISD::FSHR nodes which is breaking a lot of the AMDGPUISD::PERM tests

@jrbyrnes it looks like AMDGPUISD::PERM matching always starts from a ISD::OR node, which have now been folded to ISD::FSHR - what is the best way to generalize the performOrCombine handling to support ISD::FSHR as well?


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D159533

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/AMDGPU/ctpop16.ll
  llvm/test/CodeGen/AMDGPU/permute_i8.ll

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