[llvm] [RISCV] Add searchable table for tune information (PR #66193)

[Wang Pengcheng via llvm-commits]

================
@@ -10,20 +10,36 @@
 // RISC-V processors supported.
 //===----------------------------------------------------------------------===//
 
+class RISCVTuneInfo {
+  bits<8> PrefFunctionAlignment = 1;
+  bits<8> PrefLoopAlignment = 1;
+}
+
+def RISCVTuneInfoTable : GenericTable {
+  let FilterClass = "RISCVTuneInfo";
+  let CppTypeName = "RISCVTuneInfo";
+  let Fields = ["Name", "PrefFunctionAlignment", "PrefLoopAlignment"];
+}
+
+def getRISCVTuneInfo : SearchIndex {
+  let Table = RISCVTuneInfoTable;
+  let Key = ["Name"];
+}
+
 class RISCVProcessorModel<string n,
                           SchedMachineModel m,
                           list<SubtargetFeature> f,
                           list<SubtargetFeature> tunef = [],
                           string default_march = "">
-      :  ProcessorModel<n, m, f, tunef> {
+      :  ProcessorModel<n, m, f, tunef>, RISCVTuneInfo {
----------------
wangpc-pp wrote:

I changed the implementation.
We don't need to define a `RISCVTuneInfo` for each processor and it will use the fault value (which is for `generic`) if no `RISCVTuneInfo` defined.
For processors in the same series, a subclass can inherit from `RISCVTuneInfo` and override the fields. And we can also override the fields in processor definitions if there are some differences in the same processor series.
It can be like:
```
class SiFive7TuneInfo: RISCVTuneInfo {
  let XXX = xxx; // Override the field in class definition.
  // ...
};

def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series",
                                       SiFive7Model,
                                       [TuneSiFive7]>, SiFive7TuneInfo;

def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
                                     SiFive7Model,
                                     [Feature64Bit,
                                      FeatureStdExtZifencei,
                                      FeatureStdExtM,
                                      FeatureStdExtA,
                                      FeatureStdExtF,
                                      FeatureStdExtD,
                                      FeatureStdExtC],
                                     [TuneSiFive7]>, SiFive7TuneInfo {
  let XXX = xxx; // Override the field in processor definition.
  // ...
}
```

https://github.com/llvm/llvm-project/pull/66193