[llvm] 4c241a9 - [InstCombine] Fold `(-1 + A) & B` into `A ? 0 : B` where A is effectively a bool

[Yingwei Zheng via llvm-commits]

Author: Yingwei Zheng
Date: 2023-09-24T19:10:47+08:00
New Revision: 4c241a9335c3046e418e1b4afc162bc576c072fd

URL: https://github.com/llvm/llvm-project/commit/4c241a9335c3046e418e1b4afc162bc576c072fd
DIFF: https://github.com/llvm/llvm-project/commit/4c241a9335c3046e418e1b4afc162bc576c072fd.diff

LOG: [InstCombine] Fold `(-1 + A) & B` into `A ? 0 : B` where A is effectively a bool

Solves issue https://github.com/llvm/llvm-project/issues/63321.

This patch explicitly folds `(-1 + A) & B` into `A ? 0 : B`. Additional trunc will be created when `A` is neither i1 nor <N x i1>.

https://alive2.llvm.org/ce/z/pWv9jJ

Reviewed By: goldstein.w.n

Differential Revision: https://reviews.llvm.org/D153148

Added: 
    

Modified: 
    llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
    llvm/test/Transforms/InstCombine/binop-cast.ll
    llvm/test/Transforms/InstCombine/rem-mul-shl.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index ca7dfa82ab5a5d7..c04fe827207fd0d 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -2654,6 +2654,18 @@ Instruction *InstCombinerImpl::visitAnd(BinaryOperator &I) {
       A->getType()->isIntOrIntVectorTy(1))
     return SelectInst::Create(A, Constant::getNullValue(Ty), B);
 
+  // (-1 + A) & B --> A ? 0 : B where A is 0/1.
+  if (match(&I, m_c_And(m_OneUse(m_Add(m_ZExtOrSelf(m_Value(A)), m_AllOnes())),
+                        m_Value(B)))) {
+    if (A->getType()->isIntOrIntVectorTy(1))
+      return SelectInst::Create(A, Constant::getNullValue(Ty), B);
+    if (computeKnownBits(A, /* Depth */ 0, &I).countMaxActiveBits() <= 1) {
+      return SelectInst::Create(
+          Builder.CreateICmpEQ(A, Constant::getNullValue(A->getType())), B,
+          Constant::getNullValue(Ty));
+    }
+  }
+
   // (iN X s>> (N-1)) & Y --> (X s< 0) ? Y : 0 -- with optional sext
   if (match(&I, m_c_And(m_OneUse(m_SExtOrSelf(
                             m_AShr(m_Value(X), m_APIntAllowUndef(C)))),

diff  --git a/llvm/test/Transforms/InstCombine/binop-cast.ll b/llvm/test/Transforms/InstCombine/binop-cast.ll
index c2cd387c90bac97..20d5814c05d3aa7 100644
--- a/llvm/test/Transforms/InstCombine/binop-cast.ll
+++ b/llvm/test/Transforms/InstCombine/binop-cast.ll
@@ -261,9 +261,8 @@ define i32 @xor_sext_to_sel_multi_use_constant_mask(i1 %y) {
 define i64 @PR63321(ptr %ptr, i64 %c) {
 ; CHECK-LABEL: @PR63321(
 ; CHECK-NEXT:    [[VAL:%.*]] = load i8, ptr [[PTR:%.*]], align 1, !range [[RNG0:![0-9]+]]
-; CHECK-NEXT:    [[RHS:%.*]] = zext i8 [[VAL]] to i64
-; CHECK-NEXT:    [[MASK:%.*]] = add nsw i64 [[RHS]], -1
-; CHECK-NEXT:    [[RES:%.*]] = and i64 [[MASK]], [[C:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i8 [[VAL]], 0
+; CHECK-NEXT:    [[RES:%.*]] = select i1 [[TMP1]], i64 [[C:%.*]], i64 0
 ; CHECK-NEXT:    ret i64 [[RES]]
 ;
   %val = load i8, ptr %ptr, align 1, !range !{i8 0, i8 2}
@@ -300,12 +299,11 @@ define i32 @and_add_bool_to_select(i1 %x, i32 %y) {
   ret i32 %res
 }
 
-; Negative test of and_add_bool_to_select
 define i32 @and_add_bool_no_fold(i32 %y) {
 ; CHECK-LABEL: @and_add_bool_no_fold(
 ; CHECK-NEXT:    [[X:%.*]] = and i32 [[Y:%.*]], 1
-; CHECK-NEXT:    [[MASK:%.*]] = add nsw i32 [[X]], -1
-; CHECK-NEXT:    [[RES:%.*]] = and i32 [[MASK]], [[Y]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[X]], 0
+; CHECK-NEXT:    [[RES:%.*]] = select i1 [[TMP1]], i32 [[Y]], i32 0
 ; CHECK-NEXT:    ret i32 [[RES]]
 ;
   %x = and i32 %y, 1

diff  --git a/llvm/test/Transforms/InstCombine/rem-mul-shl.ll b/llvm/test/Transforms/InstCombine/rem-mul-shl.ll
index 257e9762e7b32cd..75f4d3f4fb07da5 100644
--- a/llvm/test/Transforms/InstCombine/rem-mul-shl.ll
+++ b/llvm/test/Transforms/InstCombine/rem-mul-shl.ll
@@ -930,10 +930,9 @@ define i32 @and_add_shl_vscale_not_power2_negative() vscale_range(1,16) {
 ; Negative test: the %sign may be 0, https://alive2.llvm.org/ce/z/WU_j4a
 define i32 @and_add_and (i32 %x) {
 ; CHECK-LABEL: @and_add_and(
-; CHECK-NEXT:    [[X1:%.*]] = lshr i32 [[X:%.*]], 7
-; CHECK-NEXT:    [[SIGN:%.*]] = and i32 [[X1]], 1
-; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[SIGN]], -1
-; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ADD]], -2147483648
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[X:%.*]], 24
+; CHECK-NEXT:    [[TMP2:%.*]] = and i32 [[TMP1]], -2147483648
+; CHECK-NEXT:    [[AND:%.*]] = xor i32 [[TMP2]], -2147483648
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
   %x1 = lshr i32 %x, 7