[llvm] e145bc4 - [gn build] Port 93fde2ea1b2c

[LLVM GN Syncbot via llvm-commits]

Author: LLVM GN Syncbot
Date: 2023-09-19T17:10:08Z
New Revision: e145bc4d7d69f86c66f479d25bb532b3725a74ee

URL: https://github.com/llvm/llvm-project/commit/e145bc4d7d69f86c66f479d25bb532b3725a74ee
DIFF: https://github.com/llvm/llvm-project/commit/e145bc4d7d69f86c66f479d25bb532b3725a74ee.diff

LOG: [gn build] Port 93fde2ea1b2c

Added: 
    

Modified: 
    llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn

Removed: 
    


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diff  --git a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
index 863b760a9028f9d..d13c07b36c96822 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
@@ -61,8 +61,8 @@ static_library("LLVMRISCVCodeGen") {
     ":RISCVGenCompressInstEmitter",
     ":RISCVGenDAGISel",
     ":RISCVGenGlobalISel",
-    ":RISCVGenO0PreLegalizeGICombiner",
     ":RISCVGenMCPseudoLowering",
+    ":RISCVGenO0PreLegalizeGICombiner",
     ":RISCVGenPreLegalizeGICombiner",
     ":RISCVGenRegisterBank",
 
@@ -92,6 +92,7 @@ static_library("LLVMRISCVCodeGen") {
     "GISel/RISCVRegisterBankInfo.cpp",
     "RISCVAsmPrinter.cpp",
     "RISCVCodeGenPrepare.cpp",
+    "RISCVDeadRegisterDefinitions.cpp",
     "RISCVExpandAtomicPseudoInsts.cpp",
     "RISCVExpandPseudoInsts.cpp",
     "RISCVFrameLowering.cpp",