[llvm] [AArch64][SVE2] Do not emit RSHRNB for large shifts (PR #66672)
David Sherwood via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 20 02:50:46 PDT 2023
================
@@ -20241,6 +20241,9 @@ static SDValue trySimplifySrlAddToRshrnb(SDValue Srl, SelectionDAG &DAG,
return SDValue();
unsigned ShiftValue = SrlOp1->getZExtValue();
+ if (ShiftValue > ResVT.getScalarSizeInBits())
----------------
david-arm wrote:
I think it's unlikely to happen, but is it worth being paranoid here and also test for the zero shift case? The instruction RSHRNB only permits shifts between 1 and the dest element bit width.
https://github.com/llvm/llvm-project/pull/66672
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