[llvm] b83a1ed - [RISCV] Only emit .option when extension is supported

[Piyou Chen via llvm-commits]

Author: Piyou Chen
Date: 2023-09-18T00:30:13-07:00
New Revision: b83a1ed594f60953519c0eed53952d1abbcf65f3

URL: https://github.com/llvm/llvm-project/commit/b83a1ed594f60953519c0eed53952d1abbcf65f3
DIFF: https://github.com/llvm/llvm-project/commit/b83a1ed594f60953519c0eed53952d1abbcf65f3.diff

LOG: [RISCV] Only emit .option when extension is supported

It maybe emit the .option directive without any follow up. Only emit the .option push/pop when there are supported extension difference between function and module.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D159399

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
    llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 1832ef50b9ad1c8..17326c68f0bd363 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -88,8 +88,7 @@ class RISCVAsmPrinter : public AsmPrinter {
   void emitEndOfAsmFile(Module &M) override;
 
   void emitFunctionEntryLabel() override;
-  void emitDirectiveOptionArch();
-  bool isSameAttribute();
+  bool emitDirectiveOptionArch();
 
 private:
   void emitAttributes();
@@ -252,7 +251,7 @@ bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
   return false;
 }
 
-void RISCVAsmPrinter::emitDirectiveOptionArch() {
+bool RISCVAsmPrinter::emitDirectiveOptionArch() {
   RISCVTargetStreamer &RTS =
       static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
   SmallVector<RISCVOptionArchArg> NeedEmitStdOptionArgs;
@@ -268,28 +267,26 @@ void RISCVAsmPrinter::emitDirectiveOptionArch() {
                                                 : RISCVOptionArchArgType::Minus;
     NeedEmitStdOptionArgs.emplace_back(Delta, Feature.Key);
   }
-  if (!NeedEmitStdOptionArgs.empty())
+  if (!NeedEmitStdOptionArgs.empty()) {
+    RTS.emitDirectiveOptionPush();
     RTS.emitDirectiveOptionArch(NeedEmitStdOptionArgs);
-}
+    return true;
+  }
 
-bool RISCVAsmPrinter::isSameAttribute() {
-  const MCSubtargetInfo &MCSTI = *TM.getMCSubtargetInfo();
-  return MCSTI.getFeatureBits() == STI->getFeatureBits();
+  return false;
 }
 
 bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   STI = &MF.getSubtarget<RISCVSubtarget>();
   RISCVTargetStreamer &RTS =
       static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
-  if (!isSameAttribute()) {
-    RTS.emitDirectiveOptionPush();
-    emitDirectiveOptionArch();
-  }
+
+  bool EmittedOptionArch = emitDirectiveOptionArch();
 
   SetupMachineFunction(MF);
   emitFunctionBody();
 
-  if (!isSameAttribute())
+  if (EmittedOptionArch)
     RTS.emitDirectiveOptionPop();
   return false;
 }

diff  --git a/llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll b/llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
index 255176efb4cd17f..d627ae9c90394eb 100644
--- a/llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
+++ b/llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
@@ -35,10 +35,10 @@ entry:
   ret void
 }
 
-; CHECK: .option push
+; CHECK-NOT: .option push
 define void @test5() "target-features"="+unaligned-scalar-mem" {
 ; CHECK-LABEL: test5
-; CHECK: .option pop
+; CHECK-NOT: .option pop
 entry:
   ret void
 }