[llvm] [RISCV] Promote SETCC and VP_SETCC of f16 vectors when only have zvfhmin (PR #66866)
Jianjian Guan via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 20 00:16:53 PDT 2023
https://github.com/jacquesguan created https://github.com/llvm/llvm-project/pull/66866
This patch implements the promotion of fp16 vectors SETCC and VP_SETCC when we only have zvfhmin but no zvfh.
>From e48ecb123f75549fb570119bc71b305276ceeacf Mon Sep 17 00:00:00 2001
From: Jianjian GUAN <jacquesguan at me.com>
Date: Wed, 20 Sep 2023 14:35:58 +0800
Subject: [PATCH] [RISCV] Promote SETCC and VP_SETCC of f16 vectors when only
have zvfhmin
---
.../SelectionDAG/LegalizeVectorOps.cpp | 36 +
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 26 +-
.../RISCV/rvv/fixed-vectors-fp-setcc.ll | 1077 +++++---
.../RISCV/rvv/fixed-vectors-setcc-fp-vp.ll | 1120 ++++++--
llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll | 2450 +++++++++++++----
llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll | 1696 +++++++++---
6 files changed, 4837 insertions(+), 1568 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index dec81475f3a88fc..2e490b0b7f38991 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -173,6 +173,12 @@ class VectorLegalizer {
/// result is truncated back to the original scalar type.
void PromoteReduction(SDNode *Node, SmallVectorImpl<SDValue> &Results);
+ /// Implements vector setcc operation promotion.
+ ///
+ /// All vector operands are promoted to a vector type with larger element
+ /// type.
+ void PromoteSETCC(SDNode *Node, SmallVectorImpl<SDValue> &Results);
+
public:
VectorLegalizer(SelectionDAG& dag) :
DAG(dag), TLI(dag.getTargetLoweringInfo()) {}
@@ -603,6 +609,31 @@ void VectorLegalizer::PromoteReduction(SDNode *Node,
Results.push_back(Res);
}
+void VectorLegalizer::PromoteSETCC(SDNode *Node,
+ SmallVectorImpl<SDValue> &Results) {
+ MVT VecVT = Node->getOperand(0).getSimpleValueType();
+ MVT NewVecVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VecVT);
+
+ unsigned ExtOp = VecVT.isFloatingPoint() ? ISD::FP_EXTEND : ISD::ANY_EXTEND;
+
+ SDLoc DL(Node);
+ SmallVector<SDValue, 4> Operands(Node->getNumOperands());
+
+ Operands[0] = DAG.getNode(ExtOp, DL, NewVecVT, Node->getOperand(0));
+ Operands[1] = DAG.getNode(ExtOp, DL, NewVecVT, Node->getOperand(1));
+ Operands[2] = Node->getOperand(2);
+
+ if (Node->getOpcode() == ISD::VP_SETCC) {
+ Operands[3] = Node->getOperand(3); // mask
+ Operands[4] = Node->getOperand(4); // evl
+ }
+
+ SDValue Res = DAG.getNode(Node->getOpcode(), DL, Node->getSimpleValueType(0),
+ Operands, Node->getFlags());
+
+ Results.push_back(Res);
+}
+
void VectorLegalizer::Promote(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
// For a few operations there is a specific concept for promotion based on
// the operand's type.
@@ -638,6 +669,11 @@ void VectorLegalizer::Promote(SDNode *Node, SmallVectorImpl<SDValue> &Results) {
// Promote the operation by extending the operand.
PromoteReduction(Node, Results);
return;
+ case ISD::VP_SETCC:
+ case ISD::SETCC:
+ // Promote the operation by extending the operand.
+ PromoteSETCC(Node, Results);
+ return;
case ISD::FP_ROUND:
case ISD::FP_EXTEND:
// These operations are used to do promotion so they can't be promoted
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f1cea6c6756f4fc..a75a9cb4f4a1599 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -824,11 +824,11 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
// TODO: support more ops.
static const unsigned ZvfhminPromoteOps[] = {
- ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD, ISD::FSUB,
- ISD::FMUL, ISD::FMA, ISD::FDIV, ISD::FSQRT,
- ISD::FABS, ISD::FNEG, ISD::FCOPYSIGN, ISD::FCEIL,
- ISD::FFLOOR, ISD::FROUND, ISD::FROUNDEVEN, ISD::FRINT,
- ISD::FNEARBYINT, ISD::IS_FPCLASS, ISD::SPLAT_VECTOR};
+ ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD, ISD::FSUB,
+ ISD::FMUL, ISD::FMA, ISD::FDIV, ISD::FSQRT,
+ ISD::FABS, ISD::FNEG, ISD::FCOPYSIGN, ISD::FCEIL,
+ ISD::FFLOOR, ISD::FROUND, ISD::FROUNDEVEN, ISD::FRINT,
+ ISD::FNEARBYINT, ISD::IS_FPCLASS, ISD::SPLAT_VECTOR, ISD::SETCC};
// TODO: support more vp ops.
static const unsigned ZvfhminPromoteVPOps[] = {
@@ -839,7 +839,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VP_FMINNUM, ISD::VP_FMAXNUM, ISD::VP_FCEIL,
ISD::VP_FFLOOR, ISD::VP_FROUND, ISD::VP_FROUNDEVEN,
ISD::VP_FCOPYSIGN, ISD::VP_FROUNDTOZERO, ISD::VP_FRINT,
- ISD::VP_FNEARBYINT};
+ ISD::VP_FNEARBYINT, ISD::VP_SETCC};
// Sets common operation actions on RVV floating-point vector types.
const auto SetCommonVFPActions = [&](MVT VT) {
@@ -5396,6 +5396,11 @@ static SDValue SplitVPOp(SDValue Op, SelectionDAG &DAG) {
DAG.SplitEVL(Op.getOperand(j), Op.getValueType(), DL);
continue;
}
+ if (!Op.getOperand(j).getValueType().isVector()) {
+ LoOperands[j] = Op.getOperand(j);
+ HiOperands[j] = Op.getOperand(j);
+ continue;
+ }
std::tie(LoOperands[j], HiOperands[j]) =
DAG.SplitVector(Op.getOperand(j), DL);
}
@@ -6083,6 +6088,11 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return DAG.getSetCC(DL, VT, RHS, LHS, CCVal);
}
+ if (Op.getOperand(0).getSimpleValueType() == MVT::nxv32f16 &&
+ (Subtarget.hasVInstructionsF16Minimal() &&
+ !Subtarget.hasVInstructionsF16()))
+ return SplitVectorOp(Op, DAG);
+
return lowerFixedLengthVectorSetccToRVV(Op, DAG);
}
case ISD::ADD:
@@ -6250,6 +6260,10 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::VP_FP_TO_UINT:
return lowerVPFPIntConvOp(Op, DAG);
case ISD::VP_SETCC:
+ if (Op.getOperand(0).getSimpleValueType() == MVT::nxv32f16 &&
+ (Subtarget.hasVInstructionsF16Minimal() &&
+ !Subtarget.hasVInstructionsF16()))
+ return SplitVPOp(Op, DAG);
if (Op.getOperand(0).getSimpleValueType().getVectorElementType() == MVT::i1)
return lowerVPSetCCMaskOp(Op, DAG);
[[fallthrough]];
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
index a7b8d8dbe330bce..a566fab1596f60c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll
@@ -1,16 +1,30 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
+; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
define void @fcmp_oeq_vv_v8f16(ptr %x, ptr %y, ptr %z) {
-; CHECK-LABEL: fcmp_oeq_vv_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vle16.v v9, (a1)
-; CHECK-NEXT: vmfeq.vv v8, v8, v9
-; CHECK-NEXT: vsm.v v8, (a2)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vv_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vle16.v v9, (a1)
+; ZVFH-NEXT: vmfeq.vv v8, v8, v9
+; ZVFH-NEXT: vsm.v v8, (a2)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vv_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a1)
+; ZVFHMIN-NEXT: vle16.v v9, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v10
+; ZVFHMIN-NEXT: vsm.v v8, (a2)
+; ZVFHMIN-NEXT: ret
%a = load <8 x half>, ptr %x
%b = load <8 x half>, ptr %y
%c = fcmp oeq <8 x half> %a, %b
@@ -19,14 +33,26 @@ define void @fcmp_oeq_vv_v8f16(ptr %x, ptr %y, ptr %z) {
}
define void @fcmp_oeq_vv_v8f16_nonans(ptr %x, ptr %y, ptr %z) {
-; CHECK-LABEL: fcmp_oeq_vv_v8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vle16.v v9, (a1)
-; CHECK-NEXT: vmfeq.vv v8, v8, v9
-; CHECK-NEXT: vsm.v v8, (a2)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vv_v8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vle16.v v9, (a1)
+; ZVFH-NEXT: vmfeq.vv v8, v8, v9
+; ZVFH-NEXT: vsm.v v8, (a2)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vv_v8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a1)
+; ZVFHMIN-NEXT: vle16.v v9, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v10
+; ZVFHMIN-NEXT: vsm.v v8, (a2)
+; ZVFHMIN-NEXT: ret
%a = load <8 x half>, ptr %x
%b = load <8 x half>, ptr %y
%c = fcmp nnan oeq <8 x half> %a, %b
@@ -135,14 +161,26 @@ define void @fcmp_ogt_vv_v2f64_nonans(ptr %x, ptr %y, ptr %z) {
}
define void @fcmp_olt_vv_v16f16(ptr %x, ptr %y, ptr %z) {
-; CHECK-LABEL: fcmp_olt_vv_v16f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vle16.v v10, (a1)
-; CHECK-NEXT: vmflt.vv v12, v8, v10
-; CHECK-NEXT: vsm.v v12, (a2)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_vv_v16f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vle16.v v10, (a1)
+; ZVFH-NEXT: vmflt.vv v12, v8, v10
+; ZVFH-NEXT: vsm.v v12, (a2)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_vv_v16f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a1)
+; ZVFHMIN-NEXT: vle16.v v10, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12
+; ZVFHMIN-NEXT: vsm.v v8, (a2)
+; ZVFHMIN-NEXT: ret
%a = load <16 x half>, ptr %x
%b = load <16 x half>, ptr %y
%c = fcmp olt <16 x half> %a, %b
@@ -151,14 +189,26 @@ define void @fcmp_olt_vv_v16f16(ptr %x, ptr %y, ptr %z) {
}
define void @fcmp_olt_vv_v16f16_nonans(ptr %x, ptr %y, ptr %z) {
-; CHECK-LABEL: fcmp_olt_vv_v16f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vle16.v v10, (a1)
-; CHECK-NEXT: vmflt.vv v12, v8, v10
-; CHECK-NEXT: vsm.v v12, (a2)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_vv_v16f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vle16.v v10, (a1)
+; ZVFH-NEXT: vmflt.vv v12, v8, v10
+; ZVFH-NEXT: vsm.v v12, (a2)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_vv_v16f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a1)
+; ZVFHMIN-NEXT: vle16.v v10, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12
+; ZVFHMIN-NEXT: vsm.v v8, (a2)
+; ZVFHMIN-NEXT: ret
%a = load <16 x half>, ptr %x
%b = load <16 x half>, ptr %y
%c = fcmp nnan olt <16 x half> %a, %b
@@ -249,16 +299,30 @@ define void @fcmp_ole_vv_v4f64_nonans(ptr %x, ptr %y, ptr %z) {
}
define void @fcmp_ule_vv_v32f16(ptr %x, ptr %y, ptr %z) {
-; CHECK-LABEL: fcmp_ule_vv_v32f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a3, 32
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vle16.v v12, (a1)
-; CHECK-NEXT: vmflt.vv v16, v12, v8
-; CHECK-NEXT: vmnot.m v8, v16
-; CHECK-NEXT: vsm.v v8, (a2)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_vv_v32f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a3, 32
+; ZVFH-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vle16.v v12, (a1)
+; ZVFH-NEXT: vmflt.vv v16, v12, v8
+; ZVFH-NEXT: vmnot.m v8, v16
+; ZVFH-NEXT: vsm.v v8, (a2)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_vv_v32f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: li a3, 32
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: vle16.v v12, (a1)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v24, v16
+; ZVFHMIN-NEXT: vmnot.m v8, v8
+; ZVFHMIN-NEXT: vsm.v v8, (a2)
+; ZVFHMIN-NEXT: ret
%a = load <32 x half>, ptr %x
%b = load <32 x half>, ptr %y
%c = fcmp ule <32 x half> %a, %b
@@ -267,15 +331,28 @@ define void @fcmp_ule_vv_v32f16(ptr %x, ptr %y, ptr %z) {
}
define void @fcmp_ule_vv_v32f16_nonans(ptr %x, ptr %y, ptr %z) {
-; CHECK-LABEL: fcmp_ule_vv_v32f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a3, 32
-; CHECK-NEXT: vsetvli zero, a3, e16, m4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vle16.v v12, (a1)
-; CHECK-NEXT: vmfle.vv v16, v8, v12
-; CHECK-NEXT: vsm.v v16, (a2)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_vv_v32f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a3, 32
+; ZVFH-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vle16.v v12, (a1)
+; ZVFH-NEXT: vmfle.vv v16, v8, v12
+; ZVFH-NEXT: vsm.v v16, (a2)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_vv_v32f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: li a3, 32
+; ZVFHMIN-NEXT: vsetvli zero, a3, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a1)
+; ZVFHMIN-NEXT: vle16.v v12, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v24, v16
+; ZVFHMIN-NEXT: vsm.v v8, (a2)
+; ZVFHMIN-NEXT: ret
%a = load <32 x half>, ptr %x
%b = load <32 x half>, ptr %y
%c = fcmp nnan ule <32 x half> %a, %b
@@ -350,16 +427,16 @@ define void @fcmp_ult_vv_v8f64_nonans(ptr %x, ptr %y, ptr %z) {
}
define void @fcmp_ugt_vv_v64f16(ptr %x, ptr %y, ptr %z) {
-; CHECK-LABEL: fcmp_ugt_vv_v64f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a3, 64
-; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vle16.v v16, (a1)
-; CHECK-NEXT: vmfle.vv v24, v8, v16
-; CHECK-NEXT: vmnot.m v8, v24
-; CHECK-NEXT: vsm.v v8, (a2)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_vv_v64f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a3, 64
+; ZVFH-NEXT: vsetvli zero, a3, e16, m8, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vle16.v v16, (a1)
+; ZVFH-NEXT: vmfle.vv v24, v8, v16
+; ZVFH-NEXT: vmnot.m v8, v24
+; ZVFH-NEXT: vsm.v v8, (a2)
+; ZVFH-NEXT: ret
%a = load <64 x half>, ptr %x
%b = load <64 x half>, ptr %y
%c = fcmp ugt <64 x half> %a, %b
@@ -368,15 +445,15 @@ define void @fcmp_ugt_vv_v64f16(ptr %x, ptr %y, ptr %z) {
}
define void @fcmp_ugt_vv_v64f16_nonans(ptr %x, ptr %y, ptr %z) {
-; CHECK-LABEL: fcmp_ugt_vv_v64f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a3, 64
-; CHECK-NEXT: vsetvli zero, a3, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vle16.v v16, (a1)
-; CHECK-NEXT: vmflt.vv v24, v16, v8
-; CHECK-NEXT: vsm.v v24, (a2)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_vv_v64f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a3, 64
+; ZVFH-NEXT: vsetvli zero, a3, e16, m8, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vle16.v v16, (a1)
+; ZVFH-NEXT: vmflt.vv v24, v16, v8
+; ZVFH-NEXT: vsm.v v24, (a2)
+; ZVFH-NEXT: ret
%a = load <64 x half>, ptr %x
%b = load <64 x half>, ptr %y
%c = fcmp nnan ugt <64 x half> %a, %b
@@ -455,25 +532,50 @@ define void @fcmp_one_vv_v8f64_nonans(ptr %x, ptr %y, ptr %z) {
}
define void @fcmp_ord_vv_v4f16(ptr %x, ptr %y, ptr %z) {
-; CHECK-LABEL: fcmp_ord_vv_v4f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a1)
-; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vmfeq.vv v8, v8, v8
-; CHECK-NEXT: vmfeq.vv v9, v9, v9
-; CHECK-NEXT: vmand.mm v0, v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; CHECK-NEXT: vmv.v.v v9, v8
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vmsne.vi v8, v9, 0
-; CHECK-NEXT: vsm.v v8, (a2)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ord_vv_v4f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a1)
+; ZVFH-NEXT: vle16.v v9, (a0)
+; ZVFH-NEXT: vmfeq.vv v8, v8, v8
+; ZVFH-NEXT: vmfeq.vv v9, v9, v9
+; ZVFH-NEXT: vmand.mm v0, v9, v8
+; ZVFH-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZVFH-NEXT: vmv.v.i v8, 0
+; ZVFH-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFH-NEXT: vmv.v.i v9, 0
+; ZVFH-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
+; ZVFH-NEXT: vmv.v.v v9, v8
+; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFH-NEXT: vmsne.vi v8, v9, 0
+; ZVFH-NEXT: vsm.v v8, (a2)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ord_vv_v4f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a1)
+; ZVFHMIN-NEXT: vle16.v v9, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v9, v10, v10
+; ZVFHMIN-NEXT: vmand.mm v0, v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZVFHMIN-NEXT: vmv.v.i v8, 0
+; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vmv.v.i v9, 0
+; ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
+; ZVFHMIN-NEXT: vmv.v.v v9, v8
+; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vmsne.vi v8, v9, 0
+; ZVFHMIN-NEXT: vsm.v v8, (a2)
+; ZVFHMIN-NEXT: ret
%a = load <4 x half>, ptr %x
%b = load <4 x half>, ptr %y
%c = fcmp ord <4 x half> %a, %b
@@ -482,25 +584,50 @@ define void @fcmp_ord_vv_v4f16(ptr %x, ptr %y, ptr %z) {
}
define void @fcmp_uno_vv_v4f16(ptr %x, ptr %y, ptr %z) {
-; CHECK-LABEL: fcmp_uno_vv_v4f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a1)
-; CHECK-NEXT: vle16.v v9, (a0)
-; CHECK-NEXT: vmfne.vv v8, v8, v8
-; CHECK-NEXT: vmfne.vv v9, v9, v9
-; CHECK-NEXT: vmor.mm v0, v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
-; CHECK-NEXT: vmv.v.v v9, v8
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vmsne.vi v8, v9, 0
-; CHECK-NEXT: vsm.v v8, (a2)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uno_vv_v4f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a1)
+; ZVFH-NEXT: vle16.v v9, (a0)
+; ZVFH-NEXT: vmfne.vv v8, v8, v8
+; ZVFH-NEXT: vmfne.vv v9, v9, v9
+; ZVFH-NEXT: vmor.mm v0, v9, v8
+; ZVFH-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFH-NEXT: vmv.v.i v8, 0
+; ZVFH-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFH-NEXT: vmv.v.i v9, 0
+; ZVFH-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; ZVFH-NEXT: vmv.v.v v9, v8
+; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFH-NEXT: vmsne.vi v8, v9, 0
+; ZVFH-NEXT: vsm.v v8, (a2)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uno_vv_v4f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a1)
+; ZVFHMIN-NEXT: vle16.v v9, (a0)
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v9, v10, v10
+; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.i v8, 0
+; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vmv.v.i v9, 0
+; ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; ZVFHMIN-NEXT: vmv.v.v v9, v8
+; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vmsne.vi v8, v9, 0
+; ZVFHMIN-NEXT: vsm.v v8, (a2)
+; ZVFHMIN-NEXT: ret
%a = load <2 x half>, ptr %x
%b = load <2 x half>, ptr %y
%c = fcmp uno <2 x half> %a, %b
@@ -509,13 +636,30 @@ define void @fcmp_uno_vv_v4f16(ptr %x, ptr %y, ptr %z) {
}
define void @fcmp_oeq_vf_v8f16(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_oeq_vf_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmfeq.vf v8, v8, fa0
-; CHECK-NEXT: vsm.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vf_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vmfeq.vf v8, v8, fa0
+; ZVFH-NEXT: vsm.v v8, (a1)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vf_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v12
+; ZVFHMIN-NEXT: vsm.v v8, (a1)
+; ZVFHMIN-NEXT: ret
%a = load <8 x half>, ptr %x
%b = insertelement <8 x half> poison, half %y, i32 0
%c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
@@ -525,13 +669,30 @@ define void @fcmp_oeq_vf_v8f16(ptr %x, half %y, ptr %z) {
}
define void @fcmp_oeq_vf_v8f16_nonans(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_oeq_vf_v8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmfeq.vf v8, v8, fa0
-; CHECK-NEXT: vsm.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vf_v8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vmfeq.vf v8, v8, fa0
+; ZVFH-NEXT: vsm.v v8, (a1)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vf_v8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v12
+; ZVFHMIN-NEXT: vsm.v v8, (a1)
+; ZVFHMIN-NEXT: ret
%a = load <8 x half>, ptr %x
%b = insertelement <8 x half> poison, half %y, i32 0
%c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
@@ -641,13 +802,30 @@ define void @fcmp_ogt_vf_v2f64_nonans(ptr %x, double %y, ptr %z) {
}
define void @fcmp_olt_vf_v16f16(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_olt_vf_v16f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmflt.vf v10, v8, fa0
-; CHECK-NEXT: vsm.v v10, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_vf_v16f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vmflt.vf v10, v8, fa0
+; ZVFH-NEXT: vsm.v v10, (a1)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_vf_v16f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16
+; ZVFHMIN-NEXT: vsm.v v8, (a1)
+; ZVFHMIN-NEXT: ret
%a = load <16 x half>, ptr %x
%b = insertelement <16 x half> poison, half %y, i32 0
%c = shufflevector <16 x half> %b, <16 x half> poison, <16 x i32> zeroinitializer
@@ -657,13 +835,30 @@ define void @fcmp_olt_vf_v16f16(ptr %x, half %y, ptr %z) {
}
define void @fcmp_olt_vf_v16f16_nonans(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_olt_vf_v16f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmflt.vf v10, v8, fa0
-; CHECK-NEXT: vsm.v v10, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_vf_v16f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vmflt.vf v10, v8, fa0
+; ZVFH-NEXT: vsm.v v10, (a1)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_vf_v16f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16
+; ZVFHMIN-NEXT: vsm.v v8, (a1)
+; ZVFHMIN-NEXT: ret
%a = load <16 x half>, ptr %x
%b = insertelement <16 x half> poison, half %y, i32 0
%c = shufflevector <16 x half> %b, <16 x half> poison, <16 x i32> zeroinitializer
@@ -755,15 +950,34 @@ define void @fcmp_ole_vf_v4f64_nonans(ptr %x, double %y, ptr %z) {
}
define void @fcmp_ule_vf_v32f16(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_ule_vf_v32f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 32
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmfgt.vf v12, v8, fa0
-; CHECK-NEXT: vmnot.m v8, v12
-; CHECK-NEXT: vsm.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_vf_v32f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a2, 32
+; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vmfgt.vf v12, v8, fa0
+; ZVFH-NEXT: vmnot.m v8, v12
+; ZVFH-NEXT: vsm.v v8, (a1)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_vf_v32f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: li a2, 32
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v16, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v24, v16
+; ZVFHMIN-NEXT: vmnot.m v8, v8
+; ZVFHMIN-NEXT: vsm.v v8, (a1)
+; ZVFHMIN-NEXT: ret
%a = load <32 x half>, ptr %x
%b = insertelement <32 x half> poison, half %y, i32 0
%c = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> zeroinitializer
@@ -773,14 +987,32 @@ define void @fcmp_ule_vf_v32f16(ptr %x, half %y, ptr %z) {
}
define void @fcmp_ule_vf_v32f16_nonans(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_ule_vf_v32f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 32
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmfle.vf v12, v8, fa0
-; CHECK-NEXT: vsm.v v12, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_vf_v32f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a2, 32
+; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vmfle.vf v12, v8, fa0
+; ZVFH-NEXT: vsm.v v12, (a1)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_vf_v32f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: li a2, 32
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v16, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v16, v24
+; ZVFHMIN-NEXT: vsm.v v8, (a1)
+; ZVFHMIN-NEXT: ret
%a = load <32 x half>, ptr %x
%b = insertelement <32 x half> poison, half %y, i32 0
%c = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> zeroinitializer
@@ -856,15 +1088,15 @@ define void @fcmp_ult_vf_v8f64_nonans(ptr %x, double %y, ptr %z) {
}
define void @fcmp_ugt_vf_v64f16(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_ugt_vf_v64f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 64
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmfle.vf v16, v8, fa0
-; CHECK-NEXT: vmnot.m v8, v16
-; CHECK-NEXT: vsm.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_vf_v64f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a2, 64
+; ZVFH-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vmfle.vf v16, v8, fa0
+; ZVFH-NEXT: vmnot.m v8, v16
+; ZVFH-NEXT: vsm.v v8, (a1)
+; ZVFH-NEXT: ret
%a = load <64 x half>, ptr %x
%b = insertelement <64 x half> poison, half %y, i32 0
%c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
@@ -874,14 +1106,14 @@ define void @fcmp_ugt_vf_v64f16(ptr %x, half %y, ptr %z) {
}
define void @fcmp_ugt_vf_v64f16_nonans(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_ugt_vf_v64f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 64
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmfgt.vf v16, v8, fa0
-; CHECK-NEXT: vsm.v v16, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_vf_v64f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a2, 64
+; ZVFH-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vmfgt.vf v16, v8, fa0
+; ZVFH-NEXT: vsm.v v16, (a1)
+; ZVFH-NEXT: ret
%a = load <64 x half>, ptr %x
%b = insertelement <64 x half> poison, half %y, i32 0
%c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
@@ -961,25 +1193,55 @@ define void @fcmp_one_vf_v8f64_nonans(ptr %x, double %y, ptr %z) {
}
define void @fcmp_ord_vf_v4f16(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_ord_vf_v4f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vf v9, v9, fa0
-; CHECK-NEXT: vmfeq.vv v8, v8, v8
-; CHECK-NEXT: vmand.mm v0, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; CHECK-NEXT: vmv.v.v v9, v8
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vmsne.vi v8, v9, 0
-; CHECK-NEXT: vsm.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ord_vf_v4f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.v.f v9, fa0
+; ZVFH-NEXT: vmfeq.vf v9, v9, fa0
+; ZVFH-NEXT: vmfeq.vv v8, v8, v8
+; ZVFH-NEXT: vmand.mm v0, v8, v9
+; ZVFH-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZVFH-NEXT: vmv.v.i v8, 0
+; ZVFH-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFH-NEXT: vmv.v.i v9, 0
+; ZVFH-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
+; ZVFH-NEXT: vmv.v.v v9, v8
+; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFH-NEXT: vmsne.vi v8, v9, 0
+; ZVFH-NEXT: vsm.v v8, (a1)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ord_vf_v4f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v9, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v9, v9, v9
+; ZVFHMIN-NEXT: vmand.mm v0, v8, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZVFHMIN-NEXT: vmv.v.i v8, 0
+; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vmv.v.i v9, 0
+; ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
+; ZVFHMIN-NEXT: vmv.v.v v9, v8
+; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vmsne.vi v8, v9, 0
+; ZVFHMIN-NEXT: vsm.v v8, (a1)
+; ZVFHMIN-NEXT: ret
%a = load <4 x half>, ptr %x
%b = insertelement <4 x half> poison, half %y, i32 0
%c = shufflevector <4 x half> %b, <4 x half> poison, <4 x i32> zeroinitializer
@@ -989,25 +1251,55 @@ define void @fcmp_ord_vf_v4f16(ptr %x, half %y, ptr %z) {
}
define void @fcmp_uno_vf_v4f16(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_uno_vf_v4f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfne.vf v9, v9, fa0
-; CHECK-NEXT: vmfne.vv v8, v8, v8
-; CHECK-NEXT: vmor.mm v0, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
-; CHECK-NEXT: vmv.v.v v9, v8
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vmsne.vi v8, v9, 0
-; CHECK-NEXT: vsm.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uno_vf_v4f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.v.f v9, fa0
+; ZVFH-NEXT: vmfne.vf v9, v9, fa0
+; ZVFH-NEXT: vmfne.vv v8, v8, v8
+; ZVFH-NEXT: vmor.mm v0, v8, v9
+; ZVFH-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFH-NEXT: vmv.v.i v8, 0
+; ZVFH-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFH-NEXT: vmv.v.i v9, 0
+; ZVFH-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; ZVFH-NEXT: vmv.v.v v9, v8
+; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFH-NEXT: vmsne.vi v8, v9, 0
+; ZVFH-NEXT: vsm.v v8, (a1)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uno_vf_v4f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v9, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v9, v9, v9
+; ZVFHMIN-NEXT: vmor.mm v0, v8, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.i v8, 0
+; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vmv.v.i v9, 0
+; ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; ZVFHMIN-NEXT: vmv.v.v v9, v8
+; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vmsne.vi v8, v9, 0
+; ZVFHMIN-NEXT: vsm.v v8, (a1)
+; ZVFHMIN-NEXT: ret
%a = load <2 x half>, ptr %x
%b = insertelement <2 x half> poison, half %y, i32 0
%c = shufflevector <2 x half> %b, <2 x half> poison, <2 x i32> zeroinitializer
@@ -1017,13 +1309,30 @@ define void @fcmp_uno_vf_v4f16(ptr %x, half %y, ptr %z) {
}
define void @fcmp_oeq_fv_v8f16(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_oeq_fv_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmfeq.vf v8, v8, fa0
-; CHECK-NEXT: vsm.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_fv_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vmfeq.vf v8, v8, fa0
+; ZVFH-NEXT: vsm.v v8, (a1)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_fv_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v10
+; ZVFHMIN-NEXT: vsm.v v8, (a1)
+; ZVFHMIN-NEXT: ret
%a = load <8 x half>, ptr %x
%b = insertelement <8 x half> poison, half %y, i32 0
%c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
@@ -1033,13 +1342,30 @@ define void @fcmp_oeq_fv_v8f16(ptr %x, half %y, ptr %z) {
}
define void @fcmp_oeq_fv_v8f16_nonans(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_oeq_fv_v8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmfeq.vf v8, v8, fa0
-; CHECK-NEXT: vsm.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_fv_v8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vmfeq.vf v8, v8, fa0
+; ZVFH-NEXT: vsm.v v8, (a1)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_fv_v8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v10
+; ZVFHMIN-NEXT: vsm.v v8, (a1)
+; ZVFHMIN-NEXT: ret
%a = load <8 x half>, ptr %x
%b = insertelement <8 x half> poison, half %y, i32 0
%c = shufflevector <8 x half> %b, <8 x half> poison, <8 x i32> zeroinitializer
@@ -1149,13 +1475,30 @@ define void @fcmp_ogt_fv_v2f64_nonans(ptr %x, double %y, ptr %z) {
}
define void @fcmp_olt_fv_v16f16(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_olt_fv_v16f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0
-; CHECK-NEXT: vsm.v v10, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_fv_v16f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vmfgt.vf v10, v8, fa0
+; ZVFH-NEXT: vsm.v v10, (a1)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_fv_v16f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12
+; ZVFHMIN-NEXT: vsm.v v8, (a1)
+; ZVFHMIN-NEXT: ret
%a = load <16 x half>, ptr %x
%b = insertelement <16 x half> poison, half %y, i32 0
%c = shufflevector <16 x half> %b, <16 x half> poison, <16 x i32> zeroinitializer
@@ -1165,13 +1508,30 @@ define void @fcmp_olt_fv_v16f16(ptr %x, half %y, ptr %z) {
}
define void @fcmp_olt_fv_v16f16_nonans(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_olt_fv_v16f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0
-; CHECK-NEXT: vsm.v v10, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_fv_v16f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vmfgt.vf v10, v8, fa0
+; ZVFH-NEXT: vsm.v v10, (a1)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_fv_v16f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12
+; ZVFHMIN-NEXT: vsm.v v8, (a1)
+; ZVFHMIN-NEXT: ret
%a = load <16 x half>, ptr %x
%b = insertelement <16 x half> poison, half %y, i32 0
%c = shufflevector <16 x half> %b, <16 x half> poison, <16 x i32> zeroinitializer
@@ -1263,15 +1623,34 @@ define void @fcmp_ole_fv_v4f64_nonans(ptr %x, double %y, ptr %z) {
}
define void @fcmp_ule_fv_v32f16(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_ule_fv_v32f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 32
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmflt.vf v12, v8, fa0
-; CHECK-NEXT: vmnot.m v8, v12
-; CHECK-NEXT: vsm.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_fv_v32f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a2, 32
+; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vmflt.vf v12, v8, fa0
+; ZVFH-NEXT: vmnot.m v8, v12
+; ZVFH-NEXT: vsm.v v8, (a1)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_fv_v32f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: li a2, 32
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v16, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v24
+; ZVFHMIN-NEXT: vmnot.m v8, v8
+; ZVFHMIN-NEXT: vsm.v v8, (a1)
+; ZVFHMIN-NEXT: ret
%a = load <32 x half>, ptr %x
%b = insertelement <32 x half> poison, half %y, i32 0
%c = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> zeroinitializer
@@ -1281,14 +1660,32 @@ define void @fcmp_ule_fv_v32f16(ptr %x, half %y, ptr %z) {
}
define void @fcmp_ule_fv_v32f16_nonans(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_ule_fv_v32f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 32
-; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmfge.vf v12, v8, fa0
-; CHECK-NEXT: vsm.v v12, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_fv_v32f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a2, 32
+; ZVFH-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vmfge.vf v12, v8, fa0
+; ZVFH-NEXT: vsm.v v12, (a1)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_fv_v32f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: li a2, 32
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v16, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
+; ZVFHMIN-NEXT: vsetvli zero, a2, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v24, v16
+; ZVFHMIN-NEXT: vsm.v v8, (a1)
+; ZVFHMIN-NEXT: ret
%a = load <32 x half>, ptr %x
%b = insertelement <32 x half> poison, half %y, i32 0
%c = shufflevector <32 x half> %b, <32 x half> poison, <32 x i32> zeroinitializer
@@ -1364,15 +1761,15 @@ define void @fcmp_ult_fv_v8f64_nonans(ptr %x, double %y, ptr %z) {
}
define void @fcmp_ugt_fv_v64f16(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_ugt_fv_v64f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 64
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmfge.vf v16, v8, fa0
-; CHECK-NEXT: vmnot.m v8, v16
-; CHECK-NEXT: vsm.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_fv_v64f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a2, 64
+; ZVFH-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vmfge.vf v16, v8, fa0
+; ZVFH-NEXT: vmnot.m v8, v16
+; ZVFH-NEXT: vsm.v v8, (a1)
+; ZVFH-NEXT: ret
%a = load <64 x half>, ptr %x
%b = insertelement <64 x half> poison, half %y, i32 0
%c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
@@ -1382,14 +1779,14 @@ define void @fcmp_ugt_fv_v64f16(ptr %x, half %y, ptr %z) {
}
define void @fcmp_ugt_fv_v64f16_nonans(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_ugt_fv_v64f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: li a2, 64
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vmflt.vf v16, v8, fa0
-; CHECK-NEXT: vsm.v v16, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_fv_v64f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: li a2, 64
+; ZVFH-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vmflt.vf v16, v8, fa0
+; ZVFH-NEXT: vsm.v v16, (a1)
+; ZVFH-NEXT: ret
%a = load <64 x half>, ptr %x
%b = insertelement <64 x half> poison, half %y, i32 0
%c = shufflevector <64 x half> %b, <64 x half> poison, <64 x i32> zeroinitializer
@@ -1469,25 +1866,55 @@ define void @fcmp_one_fv_v8f64_nonans(ptr %x, double %y, ptr %z) {
}
define void @fcmp_ord_fv_v4f16(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_ord_fv_v4f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfeq.vf v9, v9, fa0
-; CHECK-NEXT: vmfeq.vv v8, v8, v8
-; CHECK-NEXT: vmand.mm v0, v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
-; CHECK-NEXT: vmv.v.v v9, v8
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vmsne.vi v8, v9, 0
-; CHECK-NEXT: vsm.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ord_fv_v4f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.v.f v9, fa0
+; ZVFH-NEXT: vmfeq.vf v9, v9, fa0
+; ZVFH-NEXT: vmfeq.vv v8, v8, v8
+; ZVFH-NEXT: vmand.mm v0, v9, v8
+; ZVFH-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZVFH-NEXT: vmv.v.i v8, 0
+; ZVFH-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFH-NEXT: vmv.v.i v9, 0
+; ZVFH-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
+; ZVFH-NEXT: vmv.v.v v9, v8
+; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFH-NEXT: vmsne.vi v8, v9, 0
+; ZVFH-NEXT: vsm.v v8, (a1)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ord_fv_v4f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v9, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v9, v9, v9
+; ZVFHMIN-NEXT: vmand.mm v0, v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
+; ZVFHMIN-NEXT: vmv.v.i v8, 0
+; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vmv.v.i v9, 0
+; ZVFHMIN-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
+; ZVFHMIN-NEXT: vmv.v.v v9, v8
+; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vmsne.vi v8, v9, 0
+; ZVFHMIN-NEXT: vsm.v v8, (a1)
+; ZVFHMIN-NEXT: ret
%a = load <4 x half>, ptr %x
%b = insertelement <4 x half> poison, half %y, i32 0
%c = shufflevector <4 x half> %b, <4 x half> poison, <4 x i32> zeroinitializer
@@ -1497,25 +1924,55 @@ define void @fcmp_ord_fv_v4f16(ptr %x, half %y, ptr %z) {
}
define void @fcmp_uno_fv_v4f16(ptr %x, half %y, ptr %z) {
-; CHECK-LABEL: fcmp_uno_fv_v4f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vle16.v v8, (a0)
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vmfne.vf v9, v9, fa0
-; CHECK-NEXT: vmfne.vv v8, v8, v8
-; CHECK-NEXT: vmor.mm v0, v9, v8
-; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
-; CHECK-NEXT: vmv.v.v v9, v8
-; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; CHECK-NEXT: vmsne.vi v8, v9, 0
-; CHECK-NEXT: vsm.v v8, (a1)
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uno_fv_v4f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFH-NEXT: vle16.v v8, (a0)
+; ZVFH-NEXT: vfmv.v.f v9, fa0
+; ZVFH-NEXT: vmfne.vf v9, v9, fa0
+; ZVFH-NEXT: vmfne.vv v8, v8, v8
+; ZVFH-NEXT: vmor.mm v0, v9, v8
+; ZVFH-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFH-NEXT: vmv.v.i v8, 0
+; ZVFH-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFH-NEXT: vmv.v.i v9, 0
+; ZVFH-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; ZVFH-NEXT: vmv.v.v v9, v8
+; ZVFH-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFH-NEXT: vmsne.vi v8, v9, 0
+; ZVFH-NEXT: vsm.v v8, (a1)
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uno_fv_v4f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vle16.v v8, (a0)
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v9, v9
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v9, v9, v9
+; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
+; ZVFHMIN-NEXT: vmv.v.i v8, 0
+; ZVFHMIN-NEXT: vmerge.vim v8, v8, 1, v0
+; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vmv.v.i v9, 0
+; ZVFHMIN-NEXT: vsetivli zero, 2, e8, mf2, tu, ma
+; ZVFHMIN-NEXT: vmv.v.v v9, v8
+; ZVFHMIN-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: vmsne.vi v8, v9, 0
+; ZVFHMIN-NEXT: vsm.v v8, (a1)
+; ZVFHMIN-NEXT: ret
%a = load <2 x half>, ptr %x
%b = insertelement <2 x half> poison, half %y, i32 0
%c = shufflevector <2 x half> %b, <2 x half> poison, <2 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
index ddc0135d6df81a9..d7b6dccba3f8a5f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll
@@ -1,17 +1,31 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+zfh,+zvfh -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+zfh,+zvfh -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+zfh,+zvfhmin -target-abi=ilp32d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
+; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+zfh,+zvfhmin -target-abi=lp64d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
declare <7 x i1> @llvm.vp.fcmp.v7f16(<7 x half>, <7 x half>, metadata, <7 x i1>, i32)
define <7 x i1> @fcmp_oeq_vv_v7f16(<7 x half> %va, <7 x half> %vb, <7 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oeq_vv_v7f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfeq.vv v0, v8, v9, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vv_v7f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfeq.vv v0, v8, v9, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vv_v7f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <7 x i1> @llvm.vp.fcmp.v7f16(<7 x half> %va, <7 x half> %vb, metadata !"oeq", <7 x i1> %m, i32 %evl)
ret <7 x i1> %v
}
@@ -19,21 +33,46 @@ define <7 x i1> @fcmp_oeq_vv_v7f16(<7 x half> %va, <7 x half> %vb, <7 x i1> %m,
declare <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half>, <8 x half>, metadata, <8 x i1>, i32)
define <8 x i1> @fcmp_oeq_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oeq_vv_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfeq.vv v0, v8, v9, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vv_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfeq.vv v0, v8, v9, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vv_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"oeq", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v
}
define <8 x i1> @fcmp_oeq_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oeq_vf_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vf_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfeq.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vf_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"oeq", <8 x i1> %m, i32 %evl)
@@ -41,11 +80,26 @@ define <8 x i1> @fcmp_oeq_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer
}
define <8 x i1> @fcmp_oeq_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oeq_vf_swap_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vf_swap_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfeq.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vf_swap_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"oeq", <8 x i1> %m, i32 %evl)
@@ -53,21 +107,46 @@ define <8 x i1> @fcmp_oeq_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i3
}
define <8 x i1> @fcmp_ogt_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ogt_vv_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmflt.vv v0, v9, v8, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ogt_vv_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmflt.vv v0, v9, v8, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ogt_vv_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ogt", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v
}
define <8 x i1> @fcmp_ogt_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ogt_vf_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ogt_vf_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfgt.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ogt_vf_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ogt", <8 x i1> %m, i32 %evl)
@@ -75,11 +154,26 @@ define <8 x i1> @fcmp_ogt_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer
}
define <8 x i1> @fcmp_ogt_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ogt_vf_swap_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ogt_vf_swap_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmflt.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ogt_vf_swap_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v10, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"ogt", <8 x i1> %m, i32 %evl)
@@ -87,21 +181,46 @@ define <8 x i1> @fcmp_ogt_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i3
}
define <8 x i1> @fcmp_oge_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oge_vv_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfle.vv v0, v9, v8, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oge_vv_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfle.vv v0, v9, v8, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oge_vv_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"oge", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v
}
define <8 x i1> @fcmp_oge_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oge_vf_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oge_vf_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfge.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oge_vf_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"oge", <8 x i1> %m, i32 %evl)
@@ -109,11 +228,26 @@ define <8 x i1> @fcmp_oge_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer
}
define <8 x i1> @fcmp_oge_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oge_vf_swap_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oge_vf_swap_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfle.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oge_vf_swap_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v10, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"oge", <8 x i1> %m, i32 %evl)
@@ -121,21 +255,46 @@ define <8 x i1> @fcmp_oge_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i3
}
define <8 x i1> @fcmp_olt_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_olt_vv_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmflt.vv v0, v8, v9, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_vv_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmflt.vv v0, v8, v9, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_vv_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"olt", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v
}
define <8 x i1> @fcmp_olt_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_olt_vf_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_vf_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmflt.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_vf_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v10, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"olt", <8 x i1> %m, i32 %evl)
@@ -143,11 +302,26 @@ define <8 x i1> @fcmp_olt_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer
}
define <8 x i1> @fcmp_olt_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_olt_vf_swap_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_vf_swap_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfgt.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_vf_swap_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"olt", <8 x i1> %m, i32 %evl)
@@ -155,21 +329,46 @@ define <8 x i1> @fcmp_olt_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i3
}
define <8 x i1> @fcmp_ole_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ole_vv_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfle.vv v0, v8, v9, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ole_vv_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfle.vv v0, v8, v9, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ole_vv_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ole", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v
}
define <8 x i1> @fcmp_ole_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ole_vf_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ole_vf_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfle.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ole_vf_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v10, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ole", <8 x i1> %m, i32 %evl)
@@ -177,11 +376,26 @@ define <8 x i1> @fcmp_ole_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer
}
define <8 x i1> @fcmp_ole_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ole_vf_swap_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ole_vf_swap_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfge.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ole_vf_swap_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"ole", <8 x i1> %m, i32 %evl)
@@ -189,25 +403,52 @@ define <8 x i1> @fcmp_ole_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i3
}
define <8 x i1> @fcmp_one_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_one_vv_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmflt.vv v10, v8, v9, v0.t
-; CHECK-NEXT: vmflt.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vmor.mm v0, v8, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_one_vv_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmflt.vv v10, v8, v9, v0.t
+; ZVFH-NEXT: vmflt.vv v8, v9, v8, v0.t
+; ZVFH-NEXT: vmor.mm v0, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_one_vv_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v9, v10, v12, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"one", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v
}
define <8 x i1> @fcmp_one_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_one_vf_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmflt.vf v9, v8, fa0, v0.t
-; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmor.mm v0, v8, v9
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_one_vf_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmflt.vf v9, v8, fa0, v0.t
+; ZVFH-NEXT: vmfgt.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmor.mm v0, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_one_vf_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v10, v12, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v9, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"one", <8 x i1> %m, i32 %evl)
@@ -215,13 +456,29 @@ define <8 x i1> @fcmp_one_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer
}
define <8 x i1> @fcmp_one_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_one_vf_swap_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfgt.vf v9, v8, fa0, v0.t
-; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmor.mm v0, v8, v9
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_one_vf_swap_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfgt.vf v9, v8, fa0, v0.t
+; ZVFH-NEXT: vmflt.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmor.mm v0, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_one_vf_swap_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v9, v10, v12, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"one", <8 x i1> %m, i32 %evl)
@@ -229,27 +486,58 @@ define <8 x i1> @fcmp_one_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i3
}
define <8 x i1> @fcmp_ord_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ord_vv_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfeq.vv v9, v9, v9, v0.t
-; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vmand.mm v0, v8, v9
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ord_vv_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfeq.vv v9, v9, v9, v0.t
+; ZVFH-NEXT: vmfeq.vv v8, v8, v8, v0.t
+; ZVFH-NEXT: vmand.mm v0, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ord_vv_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v9, v10, v10, v0.t
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmand.mm v0, v8, v9
+; ZVFHMIN-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ord", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v
}
define <8 x i1> @fcmp_ord_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ord_vf_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
-; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vmand.mm v0, v8, v9
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ord_vf_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFH-NEXT: vfmv.v.f v9, fa0
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfeq.vf v9, v9, fa0, v0.t
+; ZVFH-NEXT: vmfeq.vv v8, v8, v8, v0.t
+; ZVFH-NEXT: vmand.mm v0, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ord_vf_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10, v0.t
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v9, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmand.mm v0, v8, v9
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ord", <8 x i1> %m, i32 %evl)
@@ -257,15 +545,33 @@ define <8 x i1> @fcmp_ord_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer
}
define <8 x i1> @fcmp_ord_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ord_vf_swap_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
-; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vmand.mm v0, v9, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ord_vf_swap_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFH-NEXT: vfmv.v.f v9, fa0
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfeq.vf v9, v9, fa0, v0.t
+; ZVFH-NEXT: vmfeq.vv v8, v8, v8, v0.t
+; ZVFH-NEXT: vmand.mm v0, v9, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ord_vf_swap_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10, v0.t
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v9, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmand.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"ord", <8 x i1> %m, i32 %evl)
@@ -273,25 +579,52 @@ define <8 x i1> @fcmp_ord_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i3
}
define <8 x i1> @fcmp_ueq_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ueq_vv_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmflt.vv v10, v8, v9, v0.t
-; CHECK-NEXT: vmflt.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vmnor.mm v0, v8, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ueq_vv_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmflt.vv v10, v8, v9, v0.t
+; ZVFH-NEXT: vmflt.vv v8, v9, v8, v0.t
+; ZVFH-NEXT: vmnor.mm v0, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ueq_vv_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v9, v10, v12, v0.t
+; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ueq", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v
}
define <8 x i1> @fcmp_ueq_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ueq_vf_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmflt.vf v9, v8, fa0, v0.t
-; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnor.mm v0, v8, v9
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ueq_vf_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmflt.vf v9, v8, fa0, v0.t
+; ZVFH-NEXT: vmfgt.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnor.mm v0, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ueq_vf_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v10, v12, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v9, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ueq", <8 x i1> %m, i32 %evl)
@@ -299,13 +632,29 @@ define <8 x i1> @fcmp_ueq_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer
}
define <8 x i1> @fcmp_ueq_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ueq_vf_swap_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfgt.vf v9, v8, fa0, v0.t
-; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnor.mm v0, v8, v9
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ueq_vf_swap_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfgt.vf v9, v8, fa0, v0.t
+; ZVFH-NEXT: vmflt.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnor.mm v0, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ueq_vf_swap_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v9, v10, v12, v0.t
+; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"ueq", <8 x i1> %m, i32 %evl)
@@ -313,23 +662,48 @@ define <8 x i1> @fcmp_ueq_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i3
}
define <8 x i1> @fcmp_ugt_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ugt_vv_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfle.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_vv_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfle.vv v8, v8, v9, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ugt_vv_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ugt", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v
}
define <8 x i1> @fcmp_ugt_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ugt_vf_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfle.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_vf_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfle.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ugt_vf_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v10, v12, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ugt", <8 x i1> %m, i32 %evl)
@@ -337,12 +711,27 @@ define <8 x i1> @fcmp_ugt_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer
}
define <8 x i1> @fcmp_ugt_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ugt_vf_swap_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfge.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_vf_swap_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfge.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ugt_vf_swap_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"ugt", <8 x i1> %m, i32 %evl)
@@ -350,23 +739,48 @@ define <8 x i1> @fcmp_ugt_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i3
}
define <8 x i1> @fcmp_uge_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uge_vv_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmflt.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uge_vv_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmflt.vv v8, v8, v9, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uge_vv_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"uge", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v
}
define <8 x i1> @fcmp_uge_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uge_vf_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uge_vf_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmflt.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uge_vf_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v10, v12, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"uge", <8 x i1> %m, i32 %evl)
@@ -374,12 +788,27 @@ define <8 x i1> @fcmp_uge_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer
}
define <8 x i1> @fcmp_uge_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uge_vf_swap_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uge_vf_swap_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfgt.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uge_vf_swap_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"uge", <8 x i1> %m, i32 %evl)
@@ -387,23 +816,48 @@ define <8 x i1> @fcmp_uge_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i3
}
define <8 x i1> @fcmp_ult_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ult_vv_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfle.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ult_vv_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfle.vv v8, v9, v8, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ult_vv_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ult", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v
}
define <8 x i1> @fcmp_ult_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ult_vf_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfge.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ult_vf_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfge.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ult_vf_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ult", <8 x i1> %m, i32 %evl)
@@ -411,12 +865,27 @@ define <8 x i1> @fcmp_ult_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer
}
define <8 x i1> @fcmp_ult_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ult_vf_swap_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfle.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ult_vf_swap_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfle.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ult_vf_swap_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v10, v12, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"ult", <8 x i1> %m, i32 %evl)
@@ -424,23 +893,48 @@ define <8 x i1> @fcmp_ult_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i3
}
define <8 x i1> @fcmp_ule_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ule_vv_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmflt.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_vv_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmflt.vv v8, v9, v8, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_vv_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ule", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v
}
define <8 x i1> @fcmp_ule_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ule_vf_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_vf_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfgt.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_vf_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ule", <8 x i1> %m, i32 %evl)
@@ -448,12 +942,27 @@ define <8 x i1> @fcmp_ule_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer
}
define <8 x i1> @fcmp_ule_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ule_vf_swap_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_vf_swap_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmflt.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_vf_swap_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v10, v12, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"ule", <8 x i1> %m, i32 %evl)
@@ -461,21 +970,46 @@ define <8 x i1> @fcmp_ule_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i3
}
define <8 x i1> @fcmp_une_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_une_vv_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfne.vv v0, v8, v9, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_une_vv_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfne.vv v0, v8, v9, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_une_vv_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"une", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v
}
define <8 x i1> @fcmp_une_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_une_vf_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfne.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_une_vf_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfne.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_une_vf_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v10, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"une", <8 x i1> %m, i32 %evl)
@@ -483,11 +1017,26 @@ define <8 x i1> @fcmp_une_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer
}
define <8 x i1> @fcmp_une_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_une_vf_swap_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfne.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_une_vf_swap_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfne.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_une_vf_swap_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"une", <8 x i1> %m, i32 %evl)
@@ -495,27 +1044,58 @@ define <8 x i1> @fcmp_une_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i3
}
define <8 x i1> @fcmp_uno_vv_v8f16(<8 x half> %va, <8 x half> %vb, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uno_vv_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfne.vv v9, v9, v9, v0.t
-; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vmor.mm v0, v8, v9
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uno_vv_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfne.vv v9, v9, v9, v0.t
+; ZVFH-NEXT: vmfne.vv v8, v8, v8, v0.t
+; ZVFH-NEXT: vmor.mm v0, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uno_vv_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v9, v10, v10, v0.t
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v8, v9
+; ZVFHMIN-NEXT: ret
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"uno", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v
}
define <8 x i1> @fcmp_uno_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uno_vf_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
-; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vmor.mm v0, v8, v9
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uno_vf_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFH-NEXT: vfmv.v.f v9, fa0
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfne.vf v9, v9, fa0, v0.t
+; ZVFH-NEXT: vmfne.vv v8, v8, v8, v0.t
+; ZVFH-NEXT: vmor.mm v0, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uno_vf_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10, v0.t
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v9, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v8, v9
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"uno", <8 x i1> %m, i32 %evl)
@@ -523,15 +1103,33 @@ define <8 x i1> @fcmp_uno_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zer
}
define <8 x i1> @fcmp_uno_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uno_vf_swap_v8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
-; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vmor.mm v0, v9, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uno_vf_swap_v8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFH-NEXT: vfmv.v.f v9, fa0
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfne.vf v9, v9, fa0, v0.t
+; ZVFH-NEXT: vmfne.vv v8, v8, v8, v0.t
+; ZVFH-NEXT: vmor.mm v0, v9, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uno_vf_swap_v8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v10, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v10
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10, v0.t
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v9, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"uno", <8 x i1> %m, i32 %evl)
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
index 40f5aeb57d176b0..734fb59e2d881f5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll
@@ -1,27 +1,53 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+v,+m,+zfh,+zvfh -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+v,+m,+zfh,+zvfh -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=ilp32d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=lp64d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
+; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
+; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfhmin,+v -target-abi=lp64d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
declare <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half>, <vscale x 1 x half>, metadata, <vscale x 1 x i1>, i32)
define <vscale x 1 x i1> @fcmp_oeq_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oeq_vv_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfeq.vv v0, v8, v9, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vv_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfeq.vv v0, v8, v9, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vv_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v10, v0.t
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"oeq", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v
}
define <vscale x 1 x i1> @fcmp_oeq_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oeq_vf_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vf_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfeq.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vf_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v8, v0.t
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"oeq", <vscale x 1 x i1> %m, i32 %evl)
@@ -29,11 +55,24 @@ define <vscale x 1 x i1> @fcmp_oeq_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
}
define <vscale x 1 x i1> @fcmp_oeq_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oeq_vf_swap_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vf_swap_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfeq.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vf_swap_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v9, v0.t
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"oeq", <vscale x 1 x i1> %m, i32 %evl)
@@ -41,21 +80,43 @@ define <vscale x 1 x i1> @fcmp_oeq_vf_swap_nxv1f16(<vscale x 1 x half> %va, half
}
define <vscale x 1 x i1> @fcmp_ogt_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ogt_vv_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmflt.vv v0, v9, v8, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ogt_vv_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmflt.vv v0, v9, v8, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ogt_vv_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v8, v10, v0.t
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ogt", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v
}
define <vscale x 1 x i1> @fcmp_ogt_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ogt_vf_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ogt_vf_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfgt.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ogt_vf_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v8, v9, v0.t
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ogt", <vscale x 1 x i1> %m, i32 %evl)
@@ -63,11 +124,24 @@ define <vscale x 1 x i1> @fcmp_ogt_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
}
define <vscale x 1 x i1> @fcmp_ogt_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ogt_vf_swap_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ogt_vf_swap_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmflt.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ogt_vf_swap_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v9, v8, v0.t
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ogt", <vscale x 1 x i1> %m, i32 %evl)
@@ -75,21 +149,43 @@ define <vscale x 1 x i1> @fcmp_ogt_vf_swap_nxv1f16(<vscale x 1 x half> %va, half
}
define <vscale x 1 x i1> @fcmp_oge_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oge_vv_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfle.vv v0, v9, v8, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oge_vv_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfle.vv v0, v9, v8, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oge_vv_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v8, v10, v0.t
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"oge", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v
}
define <vscale x 1 x i1> @fcmp_oge_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oge_vf_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oge_vf_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfge.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oge_vf_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v8, v9, v0.t
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"oge", <vscale x 1 x i1> %m, i32 %evl)
@@ -97,11 +193,24 @@ define <vscale x 1 x i1> @fcmp_oge_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
}
define <vscale x 1 x i1> @fcmp_oge_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oge_vf_swap_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oge_vf_swap_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfle.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oge_vf_swap_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v9, v8, v0.t
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"oge", <vscale x 1 x i1> %m, i32 %evl)
@@ -109,21 +218,43 @@ define <vscale x 1 x i1> @fcmp_oge_vf_swap_nxv1f16(<vscale x 1 x half> %va, half
}
define <vscale x 1 x i1> @fcmp_olt_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_olt_vv_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmflt.vv v0, v8, v9, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_vv_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmflt.vv v0, v8, v9, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_vv_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v9, v10, v0.t
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"olt", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v
}
define <vscale x 1 x i1> @fcmp_olt_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_olt_vf_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmflt.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_vf_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmflt.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_vf_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v9, v8, v0.t
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"olt", <vscale x 1 x i1> %m, i32 %evl)
@@ -131,11 +262,24 @@ define <vscale x 1 x i1> @fcmp_olt_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
}
define <vscale x 1 x i1> @fcmp_olt_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_olt_vf_swap_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_vf_swap_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfgt.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_vf_swap_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v8, v9, v0.t
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"olt", <vscale x 1 x i1> %m, i32 %evl)
@@ -143,21 +287,43 @@ define <vscale x 1 x i1> @fcmp_olt_vf_swap_nxv1f16(<vscale x 1 x half> %va, half
}
define <vscale x 1 x i1> @fcmp_ole_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ole_vv_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfle.vv v0, v8, v9, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ole_vv_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfle.vv v0, v8, v9, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ole_vv_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v9, v10, v0.t
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ole", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v
}
define <vscale x 1 x i1> @fcmp_ole_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ole_vf_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfle.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ole_vf_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfle.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ole_vf_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v9, v8, v0.t
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ole", <vscale x 1 x i1> %m, i32 %evl)
@@ -165,11 +331,24 @@ define <vscale x 1 x i1> @fcmp_ole_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
}
define <vscale x 1 x i1> @fcmp_ole_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ole_vf_swap_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfge.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ole_vf_swap_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfge.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ole_vf_swap_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v8, v9, v0.t
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ole", <vscale x 1 x i1> %m, i32 %evl)
@@ -177,25 +356,51 @@ define <vscale x 1 x i1> @fcmp_ole_vf_swap_nxv1f16(<vscale x 1 x half> %va, half
}
define <vscale x 1 x i1> @fcmp_one_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_one_vv_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmflt.vv v10, v8, v9, v0.t
-; CHECK-NEXT: vmflt.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vmor.mm v0, v8, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_one_vv_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmflt.vv v10, v8, v9, v0.t
+; ZVFH-NEXT: vmflt.vv v8, v9, v8, v0.t
+; ZVFH-NEXT: vmor.mm v0, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_one_vv_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v9, v10, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v9, v10, v9, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"one", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v
}
define <vscale x 1 x i1> @fcmp_one_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_one_vf_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmflt.vf v9, v8, fa0, v0.t
-; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmor.mm v0, v8, v9
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_one_vf_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmflt.vf v9, v8, fa0, v0.t
+; ZVFH-NEXT: vmfgt.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmor.mm v0, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_one_vf_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v10, v9, v8, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v8, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v8, v10
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"one", <vscale x 1 x i1> %m, i32 %evl)
@@ -203,13 +408,28 @@ define <vscale x 1 x i1> @fcmp_one_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
}
define <vscale x 1 x i1> @fcmp_one_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_one_vf_swap_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfgt.vf v9, v8, fa0, v0.t
-; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmor.mm v0, v8, v9
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_one_vf_swap_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfgt.vf v9, v8, fa0, v0.t
+; ZVFH-NEXT: vmflt.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmor.mm v0, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_one_vf_swap_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v10, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v8, v9, v8, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v8, v10
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"one", <vscale x 1 x i1> %m, i32 %evl)
@@ -217,27 +437,57 @@ define <vscale x 1 x i1> @fcmp_one_vf_swap_nxv1f16(<vscale x 1 x half> %va, half
}
define <vscale x 1 x i1> @fcmp_ord_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ord_vv_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfeq.vv v9, v9, v9, v0.t
-; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vmand.mm v0, v8, v9
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ord_vv_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfeq.vv v9, v9, v9, v0.t
+; ZVFH-NEXT: vmfeq.vv v8, v8, v8, v0.t
+; ZVFH-NEXT: vmand.mm v0, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ord_vv_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v9, v10, v10, v0.t
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmand.mm v0, v8, v9
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v
}
define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ord_vf_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
-; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vmand.mm v0, v8, v9
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ord_vf_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFH-NEXT: vfmv.v.f v9, fa0
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfeq.vf v9, v9, fa0, v0.t
+; ZVFH-NEXT: vmfeq.vv v8, v8, v8, v0.t
+; ZVFH-NEXT: vmand.mm v0, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ord_vf_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v9, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v9, v9, v9, v0.t
+; ZVFHMIN-NEXT: vmand.mm v0, v8, v9
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl)
@@ -245,15 +495,32 @@ define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
}
define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ord_vf_swap_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
-; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vmand.mm v0, v9, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ord_vf_swap_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFH-NEXT: vfmv.v.f v9, fa0
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfeq.vf v9, v9, fa0, v0.t
+; ZVFH-NEXT: vmfeq.vv v8, v8, v8, v0.t
+; ZVFH-NEXT: vmand.mm v0, v9, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ord_vf_swap_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v9, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v9, v9, v9, v0.t
+; ZVFHMIN-NEXT: vmand.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl)
@@ -261,25 +528,51 @@ define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1f16(<vscale x 1 x half> %va, half
}
define <vscale x 1 x i1> @fcmp_ueq_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ueq_vv_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmflt.vv v10, v8, v9, v0.t
-; CHECK-NEXT: vmflt.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vmnor.mm v0, v8, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ueq_vv_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmflt.vv v10, v8, v9, v0.t
+; ZVFH-NEXT: vmflt.vv v8, v9, v8, v0.t
+; ZVFH-NEXT: vmnor.mm v0, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ueq_vv_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v9, v10, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v9, v10, v9, v0.t
+; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ueq", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v
}
define <vscale x 1 x i1> @fcmp_ueq_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ueq_vf_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmflt.vf v9, v8, fa0, v0.t
-; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnor.mm v0, v8, v9
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ueq_vf_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmflt.vf v9, v8, fa0, v0.t
+; ZVFH-NEXT: vmfgt.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnor.mm v0, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ueq_vf_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v10, v9, v8, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v8, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmnor.mm v0, v8, v10
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ueq", <vscale x 1 x i1> %m, i32 %evl)
@@ -287,13 +580,28 @@ define <vscale x 1 x i1> @fcmp_ueq_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
}
define <vscale x 1 x i1> @fcmp_ueq_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ueq_vf_swap_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfgt.vf v9, v8, fa0, v0.t
-; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnor.mm v0, v8, v9
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ueq_vf_swap_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfgt.vf v9, v8, fa0, v0.t
+; ZVFH-NEXT: vmflt.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnor.mm v0, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ueq_vf_swap_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v10, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v8, v9, v8, v0.t
+; ZVFHMIN-NEXT: vmnor.mm v0, v8, v10
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ueq", <vscale x 1 x i1> %m, i32 %evl)
@@ -301,23 +609,47 @@ define <vscale x 1 x i1> @fcmp_ueq_vf_swap_nxv1f16(<vscale x 1 x half> %va, half
}
define <vscale x 1 x i1> @fcmp_ugt_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ugt_vv_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfle.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_vv_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfle.vv v8, v8, v9, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ugt_vv_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v9, v10, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v
}
define <vscale x 1 x i1> @fcmp_ugt_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ugt_vf_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfle.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_vf_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfle.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ugt_vf_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v9, v8, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl)
@@ -325,12 +657,26 @@ define <vscale x 1 x i1> @fcmp_ugt_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
}
define <vscale x 1 x i1> @fcmp_ugt_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ugt_vf_swap_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfge.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_vf_swap_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfge.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ugt_vf_swap_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ugt", <vscale x 1 x i1> %m, i32 %evl)
@@ -338,23 +684,47 @@ define <vscale x 1 x i1> @fcmp_ugt_vf_swap_nxv1f16(<vscale x 1 x half> %va, half
}
define <vscale x 1 x i1> @fcmp_uge_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uge_vv_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmflt.vv v8, v8, v9, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uge_vv_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmflt.vv v8, v8, v9, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uge_vv_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v9, v10, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v
}
define <vscale x 1 x i1> @fcmp_uge_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uge_vf_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uge_vf_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmflt.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uge_vf_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v9, v8, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl)
@@ -362,12 +732,26 @@ define <vscale x 1 x i1> @fcmp_uge_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
}
define <vscale x 1 x i1> @fcmp_uge_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uge_vf_swap_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uge_vf_swap_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfgt.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uge_vf_swap_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"uge", <vscale x 1 x i1> %m, i32 %evl)
@@ -375,23 +759,47 @@ define <vscale x 1 x i1> @fcmp_uge_vf_swap_nxv1f16(<vscale x 1 x half> %va, half
}
define <vscale x 1 x i1> @fcmp_ult_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ult_vv_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfle.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ult_vv_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfle.vv v8, v9, v8, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ult_vv_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v8, v10, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v
}
define <vscale x 1 x i1> @fcmp_ult_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ult_vf_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfge.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ult_vf_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfge.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ult_vf_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl)
@@ -399,12 +807,26 @@ define <vscale x 1 x i1> @fcmp_ult_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
}
define <vscale x 1 x i1> @fcmp_ult_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ult_vf_swap_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfle.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ult_vf_swap_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfle.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ult_vf_swap_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v9, v8, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ult", <vscale x 1 x i1> %m, i32 %evl)
@@ -412,23 +834,47 @@ define <vscale x 1 x i1> @fcmp_ult_vf_swap_nxv1f16(<vscale x 1 x half> %va, half
}
define <vscale x 1 x i1> @fcmp_ule_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ule_vv_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmflt.vv v8, v9, v8, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_vv_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmflt.vv v8, v9, v8, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_vv_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v8, v10, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ule", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v
}
define <vscale x 1 x i1> @fcmp_ule_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ule_vf_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfgt.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_vf_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfgt.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_vf_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v8, v9, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ule", <vscale x 1 x i1> %m, i32 %evl)
@@ -436,12 +882,26 @@ define <vscale x 1 x i1> @fcmp_ule_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
}
define <vscale x 1 x i1> @fcmp_ule_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ule_vf_swap_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmflt.vf v8, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_vf_swap_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmflt.vf v8, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_vf_swap_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v9, v8, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ule", <vscale x 1 x i1> %m, i32 %evl)
@@ -449,21 +909,43 @@ define <vscale x 1 x i1> @fcmp_ule_vf_swap_nxv1f16(<vscale x 1 x half> %va, half
}
define <vscale x 1 x i1> @fcmp_une_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_une_vv_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfne.vv v0, v8, v9, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_une_vv_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfne.vv v0, v8, v9, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_une_vv_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v0, v9, v10, v0.t
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"une", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v
}
define <vscale x 1 x i1> @fcmp_une_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_une_vf_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfne.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_une_vf_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfne.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_une_vf_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v0, v9, v8, v0.t
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"une", <vscale x 1 x i1> %m, i32 %evl)
@@ -471,11 +953,24 @@ define <vscale x 1 x i1> @fcmp_une_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
}
define <vscale x 1 x i1> @fcmp_une_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_une_vf_swap_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfne.vf v0, v8, fa0, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_une_vf_swap_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfne.vf v0, v8, fa0, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_une_vf_swap_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v0, v8, v9, v0.t
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"une", <vscale x 1 x i1> %m, i32 %evl)
@@ -483,27 +978,57 @@ define <vscale x 1 x i1> @fcmp_une_vf_swap_nxv1f16(<vscale x 1 x half> %va, half
}
define <vscale x 1 x i1> @fcmp_uno_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uno_vv_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfne.vv v9, v9, v9, v0.t
-; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vmor.mm v0, v8, v9
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uno_vv_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfne.vv v9, v9, v9, v0.t
+; ZVFH-NEXT: vmfne.vv v8, v8, v8, v0.t
+; ZVFH-NEXT: vmor.mm v0, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uno_vv_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v9, v10, v10, v0.t
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v8, v9
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v
}
define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uno_vf_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
-; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vmor.mm v0, v8, v9
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uno_vf_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFH-NEXT: vfmv.v.f v9, fa0
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfne.vf v9, v9, fa0, v0.t
+; ZVFH-NEXT: vmfne.vv v8, v8, v8, v0.t
+; ZVFH-NEXT: vmor.mm v0, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uno_vf_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v9, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v9, v9, v9, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v8, v9
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl)
@@ -511,15 +1036,32 @@ define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f16(<vscale x 1 x half> %va, half %b,
}
define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uno_vf_swap_nxv1f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vfmv.v.f v9, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
-; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vmor.mm v0, v9, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uno_vf_swap_nxv1f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFH-NEXT: vfmv.v.f v9, fa0
+; ZVFH-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
+; ZVFH-NEXT: vmfne.vf v9, v9, fa0, v0.t
+; ZVFH-NEXT: vmfne.vv v8, v8, v8, v0.t
+; ZVFH-NEXT: vmor.mm v0, v9, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uno_vf_swap_nxv1f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v9, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v9, v9, v0.t
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v9, v9, v9, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl)
@@ -529,11 +1071,21 @@ define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1f16(<vscale x 1 x half> %va, half
declare <vscale x 3 x i1> @llvm.vp.fcmp.nxv3f16(<vscale x 3 x half>, <vscale x 3 x half>, metadata, <vscale x 3 x i1>, i32)
define <vscale x 3 x i1> @fcmp_oeq_vv_nxv3f16(<vscale x 3 x half> %va, <vscale x 3 x half> %vb, <vscale x 3 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oeq_vv_nxv3f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmfeq.vv v0, v8, v9, v0.t
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vv_nxv3f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma
+; ZVFH-NEXT: vmfeq.vv v0, v8, v9, v0.t
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vv_nxv3f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v10, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 3 x i1> @llvm.vp.fcmp.nxv3f16(<vscale x 3 x half> %va, <vscale x 3 x half> %vb, metadata !"oeq", <vscale x 3 x i1> %m, i32 %evl)
ret <vscale x 3 x i1> %v
}
@@ -541,23 +1093,47 @@ define <vscale x 3 x i1> @fcmp_oeq_vv_nxv3f16(<vscale x 3 x half> %va, <vscale x
declare <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, metadata, <vscale x 8 x i1>, i32)
define <vscale x 8 x i1> @fcmp_oeq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oeq_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfeq.vv v12, v8, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfeq.vv v12, v8, v10, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"oeq", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v
}
define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oeq_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfeq.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"oeq", <vscale x 8 x i1> %m, i32 %evl)
@@ -565,12 +1141,26 @@ define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
}
define <vscale x 8 x i1> @fcmp_oeq_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oeq_vf_swap_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vf_swap_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfeq.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vf_swap_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"oeq", <vscale x 8 x i1> %m, i32 %evl)
@@ -578,23 +1168,47 @@ define <vscale x 8 x i1> @fcmp_oeq_vf_swap_nxv8f16(<vscale x 8 x half> %va, half
}
define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ogt_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vv v12, v10, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ogt_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vv v12, v10, v8, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ogt_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ogt", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v
}
define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ogt_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ogt_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfgt.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ogt_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ogt", <vscale x 8 x i1> %m, i32 %evl)
@@ -602,12 +1216,26 @@ define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
}
define <vscale x 8 x i1> @fcmp_ogt_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ogt_vf_swap_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ogt_vf_swap_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ogt_vf_swap_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ogt", <vscale x 8 x i1> %m, i32 %evl)
@@ -615,23 +1243,47 @@ define <vscale x 8 x i1> @fcmp_ogt_vf_swap_nxv8f16(<vscale x 8 x half> %va, half
}
define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oge_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vv v12, v10, v8, v0.t
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oge_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vv v12, v10, v8, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oge_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"oge", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v
}
define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oge_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oge_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfge.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oge_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"oge", <vscale x 8 x i1> %m, i32 %evl)
@@ -639,12 +1291,26 @@ define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
}
define <vscale x 8 x i1> @fcmp_oge_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oge_vf_swap_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oge_vf_swap_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oge_vf_swap_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v12, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"oge", <vscale x 8 x i1> %m, i32 %evl)
@@ -652,23 +1318,47 @@ define <vscale x 8 x i1> @fcmp_oge_vf_swap_nxv8f16(<vscale x 8 x half> %va, half
}
define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_olt_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vv v12, v8, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vv v12, v8, v10, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"olt", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v
}
define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_olt_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"olt", <vscale x 8 x i1> %m, i32 %evl)
@@ -676,12 +1366,26 @@ define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
}
define <vscale x 8 x i1> @fcmp_olt_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_olt_vf_swap_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_vf_swap_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfgt.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_vf_swap_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"olt", <vscale x 8 x i1> %m, i32 %evl)
@@ -689,23 +1393,47 @@ define <vscale x 8 x i1> @fcmp_olt_vf_swap_nxv8f16(<vscale x 8 x half> %va, half
}
define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ole_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vv v12, v8, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ole_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vv v12, v8, v10, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ole_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ole", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v
}
define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ole_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ole_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ole_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v12, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ole", <vscale x 8 x i1> %m, i32 %evl)
@@ -713,12 +1441,26 @@ define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
}
define <vscale x 8 x i1> @fcmp_ole_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ole_vf_swap_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ole_vf_swap_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfge.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ole_vf_swap_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ole", <vscale x 8 x i1> %m, i32 %evl)
@@ -726,25 +1468,51 @@ define <vscale x 8 x i1> @fcmp_ole_vf_swap_nxv8f16(<vscale x 8 x half> %va, half
}
define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_one_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vv v12, v8, v10, v0.t
-; CHECK-NEXT: vmflt.vv v13, v10, v8, v0.t
-; CHECK-NEXT: vmor.mm v0, v13, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_one_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vv v12, v8, v10, v0.t
+; ZVFH-NEXT: vmflt.vv v13, v10, v8, v0.t
+; ZVFH-NEXT: vmor.mm v0, v13, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_one_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v9, v12, v16, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"one", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v
}
define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_one_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmor.mm v0, v11, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_one_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmfgt.vf v11, v8, fa0, v0.t
+; ZVFH-NEXT: vmor.mm v0, v11, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_one_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v9, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"one", <vscale x 8 x i1> %m, i32 %evl)
@@ -752,13 +1520,28 @@ define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
}
define <vscale x 8 x i1> @fcmp_one_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_one_vf_swap_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmor.mm v0, v11, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_one_vf_swap_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfgt.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmflt.vf v11, v8, fa0, v0.t
+; ZVFH-NEXT: vmor.mm v0, v11, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_one_vf_swap_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v9, v12, v16, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"one", <vscale x 8 x i1> %m, i32 %evl)
@@ -766,27 +1549,57 @@ define <vscale x 8 x i1> @fcmp_one_vf_swap_nxv8f16(<vscale x 8 x half> %va, half
}
define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ord_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfeq.vv v12, v10, v10, v0.t
-; CHECK-NEXT: vmfeq.vv v10, v8, v8, v0.t
-; CHECK-NEXT: vmand.mm v0, v10, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ord_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfeq.vv v12, v10, v10, v0.t
+; ZVFH-NEXT: vmfeq.vv v10, v8, v8, v0.t
+; ZVFH-NEXT: vmand.mm v0, v10, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ord_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v10, v12, v12, v0.t
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t
+; ZVFHMIN-NEXT: vmand.mm v0, v8, v10
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v
}
define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ord_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfmv.v.f v10, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfeq.vf v12, v10, fa0, v0.t
-; CHECK-NEXT: vmfeq.vv v10, v8, v8, v0.t
-; CHECK-NEXT: vmand.mm v0, v10, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ord_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vfmv.v.f v10, fa0
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfeq.vf v12, v10, fa0, v0.t
+; ZVFH-NEXT: vmfeq.vv v10, v8, v8, v0.t
+; ZVFH-NEXT: vmand.mm v0, v10, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ord_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v9, v12, v12, v0.t
+; ZVFHMIN-NEXT: vmand.mm v0, v8, v9
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl)
@@ -794,15 +1607,32 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
}
define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ord_vf_swap_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfmv.v.f v10, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfeq.vf v12, v10, fa0, v0.t
-; CHECK-NEXT: vmfeq.vv v10, v8, v8, v0.t
-; CHECK-NEXT: vmand.mm v0, v12, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ord_vf_swap_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vfmv.v.f v10, fa0
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfeq.vf v12, v10, fa0, v0.t
+; ZVFH-NEXT: vmfeq.vv v10, v8, v8, v0.t
+; ZVFH-NEXT: vmand.mm v0, v12, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ord_vf_swap_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12, v0.t
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v9, v12, v12, v0.t
+; ZVFHMIN-NEXT: vmand.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl)
@@ -810,25 +1640,51 @@ define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8f16(<vscale x 8 x half> %va, half
}
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ueq_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vv v12, v8, v10, v0.t
-; CHECK-NEXT: vmflt.vv v13, v10, v8, v0.t
-; CHECK-NEXT: vmnor.mm v0, v13, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ueq_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vv v12, v8, v10, v0.t
+; ZVFH-NEXT: vmflt.vv v13, v10, v8, v0.t
+; ZVFH-NEXT: vmnor.mm v0, v13, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ueq_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v9, v12, v16, v0.t
+; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ueq", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v
}
define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ueq_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmnor.mm v0, v11, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ueq_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmfgt.vf v11, v8, fa0, v0.t
+; ZVFH-NEXT: vmnor.mm v0, v11, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ueq_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v9, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ueq", <vscale x 8 x i1> %m, i32 %evl)
@@ -836,13 +1692,28 @@ define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
}
define <vscale x 8 x i1> @fcmp_ueq_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ueq_vf_swap_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
-; CHECK-NEXT: vmnor.mm v0, v11, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ueq_vf_swap_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfgt.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmflt.vf v11, v8, fa0, v0.t
+; ZVFH-NEXT: vmnor.mm v0, v11, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ueq_vf_swap_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmflt.vv v9, v12, v16, v0.t
+; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ueq", <vscale x 8 x i1> %m, i32 %evl)
@@ -850,23 +1721,47 @@ define <vscale x 8 x i1> @fcmp_ueq_vf_swap_nxv8f16(<vscale x 8 x half> %va, half
}
define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ugt_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vv v12, v8, v10, v0.t
-; CHECK-NEXT: vmnot.m v0, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vv v12, v8, v10, v0.t
+; ZVFH-NEXT: vmnot.m v0, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ugt_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ugt", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v
}
define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ugt_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ugt_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v12, v16, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ugt", <vscale x 8 x i1> %m, i32 %evl)
@@ -874,12 +1769,26 @@ define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
}
define <vscale x 8 x i1> @fcmp_ugt_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ugt_vf_swap_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_vf_swap_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfge.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ugt_vf_swap_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ugt", <vscale x 8 x i1> %m, i32 %evl)
@@ -887,23 +1796,47 @@ define <vscale x 8 x i1> @fcmp_ugt_vf_swap_nxv8f16(<vscale x 8 x half> %va, half
}
define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uge_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vv v12, v8, v10, v0.t
-; CHECK-NEXT: vmnot.m v0, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uge_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vv v12, v8, v10, v0.t
+; ZVFH-NEXT: vmnot.m v0, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uge_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v
}
define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uge_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uge_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uge_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl)
@@ -911,12 +1844,26 @@ define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
}
define <vscale x 8 x i1> @fcmp_uge_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uge_vf_swap_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uge_vf_swap_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfgt.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uge_vf_swap_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"uge", <vscale x 8 x i1> %m, i32 %evl)
@@ -924,23 +1871,47 @@ define <vscale x 8 x i1> @fcmp_uge_vf_swap_nxv8f16(<vscale x 8 x half> %va, half
}
define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ult_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vv v12, v10, v8, v0.t
-; CHECK-NEXT: vmnot.m v0, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ult_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vv v12, v10, v8, v0.t
+; ZVFH-NEXT: vmnot.m v0, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ult_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ult", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v
}
define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ult_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ult_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfge.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ult_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ult", <vscale x 8 x i1> %m, i32 %evl)
@@ -948,12 +1919,26 @@ define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
}
define <vscale x 8 x i1> @fcmp_ult_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ult_vf_swap_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ult_vf_swap_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ult_vf_swap_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v12, v16, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ult", <vscale x 8 x i1> %m, i32 %evl)
@@ -961,23 +1946,47 @@ define <vscale x 8 x i1> @fcmp_ult_vf_swap_nxv8f16(<vscale x 8 x half> %va, half
}
define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ule_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vv v12, v10, v8, v0.t
-; CHECK-NEXT: vmnot.m v0, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vv v12, v10, v8, v0.t
+; ZVFH-NEXT: vmnot.m v0, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ule", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v
}
define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ule_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfgt.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ule", <vscale x 8 x i1> %m, i32 %evl)
@@ -985,12 +1994,26 @@ define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
}
define <vscale x 8 x i1> @fcmp_ule_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_ule_vf_swap_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmnot.m v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_vf_swap_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmnot.m v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_vf_swap_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16, v0.t
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ule", <vscale x 8 x i1> %m, i32 %evl)
@@ -998,23 +2021,47 @@ define <vscale x 8 x i1> @fcmp_ule_vf_swap_nxv8f16(<vscale x 8 x half> %va, half
}
define <vscale x 8 x i1> @fcmp_une_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_une_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfne.vv v12, v8, v10, v0.t
-; CHECK-NEXT: vmv1r.v v0, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_une_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfne.vv v12, v8, v10, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_une_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"une", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v
}
define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_une_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_une_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfne.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_une_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v12, v16, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"une", <vscale x 8 x i1> %m, i32 %evl)
@@ -1022,12 +2069,26 @@ define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
}
define <vscale x 8 x i1> @fcmp_une_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_une_vf_swap_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_une_vf_swap_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfne.vf v10, v8, fa0, v0.t
+; ZVFH-NEXT: vmv1r.v v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_une_vf_swap_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v16, v12, v0.t
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"une", <vscale x 8 x i1> %m, i32 %evl)
@@ -1035,27 +2096,57 @@ define <vscale x 8 x i1> @fcmp_une_vf_swap_nxv8f16(<vscale x 8 x half> %va, half
}
define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uno_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfne.vv v12, v10, v10, v0.t
-; CHECK-NEXT: vmfne.vv v10, v8, v8, v0.t
-; CHECK-NEXT: vmor.mm v0, v10, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uno_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfne.vv v12, v10, v10, v0.t
+; ZVFH-NEXT: vmfne.vv v10, v8, v8, v0.t
+; ZVFH-NEXT: vmor.mm v0, v10, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uno_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v10, v12, v12, v0.t
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v8, v10
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v
}
define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uno_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfmv.v.f v10, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfne.vf v12, v10, fa0, v0.t
-; CHECK-NEXT: vmfne.vv v10, v8, v8, v0.t
-; CHECK-NEXT: vmor.mm v0, v10, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uno_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vfmv.v.f v10, fa0
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfne.vf v12, v10, fa0, v0.t
+; ZVFH-NEXT: vmfne.vv v10, v8, v8, v0.t
+; ZVFH-NEXT: vmor.mm v0, v10, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uno_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12, v0.t
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v9, v12, v12, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v8, v9
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl)
@@ -1063,15 +2154,32 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b,
}
define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_uno_vf_swap_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfmv.v.f v10, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmfne.vf v12, v10, fa0, v0.t
-; CHECK-NEXT: vmfne.vv v10, v8, v8, v0.t
-; CHECK-NEXT: vmor.mm v0, v12, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uno_vf_swap_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vfmv.v.f v10, fa0
+; ZVFH-NEXT: vsetvli zero, a0, e16, m2, ta, ma
+; ZVFH-NEXT: vmfne.vf v12, v10, fa0, v0.t
+; ZVFH-NEXT: vmfne.vv v10, v8, v8, v0.t
+; ZVFH-NEXT: vmor.mm v0, v12, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uno_vf_swap_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12, v0.t
+; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v9, v12, v12, v0.t
+; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl)
@@ -1081,60 +2189,224 @@ define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8f16(<vscale x 8 x half> %va, half
declare <vscale x 64 x i1> @llvm.vp.fcmp.nxv64f16(<vscale x 64 x half>, <vscale x 64 x half>, metadata, <vscale x 64 x i1>, i32)
define <vscale x 64 x i1> @fcmp_oeq_vv_nxv64f16(<vscale x 64 x half> %va, <vscale x 64 x half> %vb, <vscale x 64 x i1> %m, i32 zeroext %evl) {
-; CHECK-LABEL: fcmp_oeq_vv_nxv64f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 4
-; CHECK-NEXT: sub sp, sp, a1
-; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
-; CHECK-NEXT: vmv1r.v v24, v0
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: slli a1, a1, 3
-; CHECK-NEXT: add a1, sp, a1
-; CHECK-NEXT: addi a1, a1, 16
-; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
-; CHECK-NEXT: csrr a1, vlenb
-; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
-; CHECK-NEXT: slli a3, a1, 3
-; CHECK-NEXT: add a3, a0, a3
-; CHECK-NEXT: vl8re16.v v8, (a3)
-; CHECK-NEXT: slli a3, a1, 2
-; CHECK-NEXT: sub a4, a2, a3
-; CHECK-NEXT: sltu a5, a2, a4
-; CHECK-NEXT: addi a5, a5, -1
-; CHECK-NEXT: and a4, a5, a4
-; CHECK-NEXT: srli a1, a1, 1
-; CHECK-NEXT: vl8re16.v v0, (a0)
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
-; CHECK-NEXT: vslidedown.vx v0, v24, a1
-; CHECK-NEXT: vsetvli zero, a4, e16, m8, ta, ma
-; CHECK-NEXT: vmfeq.vv v1, v16, v8, v0.t
-; CHECK-NEXT: bltu a2, a3, .LBB85_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: mv a2, a3
-; CHECK-NEXT: .LBB85_2:
-; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
-; CHECK-NEXT: vmv1r.v v0, v24
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 3
-; CHECK-NEXT: add a0, sp, a0
-; CHECK-NEXT: addi a0, a0, 16
-; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT: addi a0, sp, 16
-; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
-; CHECK-NEXT: vmfeq.vv v16, v8, v24, v0.t
-; CHECK-NEXT: add a0, a1, a1
-; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
-; CHECK-NEXT: vslideup.vx v16, v1, a1
-; CHECK-NEXT: vmv1r.v v0, v16
-; CHECK-NEXT: csrr a0, vlenb
-; CHECK-NEXT: slli a0, a0, 4
-; CHECK-NEXT: add sp, sp, a0
-; CHECK-NEXT: addi sp, sp, 16
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vv_nxv64f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: addi sp, sp, -16
+; ZVFH-NEXT: .cfi_def_cfa_offset 16
+; ZVFH-NEXT: csrr a1, vlenb
+; ZVFH-NEXT: slli a1, a1, 4
+; ZVFH-NEXT: sub sp, sp, a1
+; ZVFH-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
+; ZVFH-NEXT: vmv1r.v v24, v0
+; ZVFH-NEXT: csrr a1, vlenb
+; ZVFH-NEXT: slli a1, a1, 3
+; ZVFH-NEXT: add a1, sp, a1
+; ZVFH-NEXT: addi a1, a1, 16
+; ZVFH-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
+; ZVFH-NEXT: csrr a1, vlenb
+; ZVFH-NEXT: vsetvli a3, zero, e8, m1, ta, ma
+; ZVFH-NEXT: slli a3, a1, 3
+; ZVFH-NEXT: add a3, a0, a3
+; ZVFH-NEXT: vl8re16.v v8, (a3)
+; ZVFH-NEXT: slli a3, a1, 2
+; ZVFH-NEXT: sub a4, a2, a3
+; ZVFH-NEXT: sltu a5, a2, a4
+; ZVFH-NEXT: addi a5, a5, -1
+; ZVFH-NEXT: and a4, a5, a4
+; ZVFH-NEXT: srli a1, a1, 1
+; ZVFH-NEXT: vl8re16.v v0, (a0)
+; ZVFH-NEXT: addi a0, sp, 16
+; ZVFH-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
+; ZVFH-NEXT: vslidedown.vx v0, v24, a1
+; ZVFH-NEXT: vsetvli zero, a4, e16, m8, ta, ma
+; ZVFH-NEXT: vmfeq.vv v1, v16, v8, v0.t
+; ZVFH-NEXT: bltu a2, a3, .LBB85_2
+; ZVFH-NEXT: # %bb.1:
+; ZVFH-NEXT: mv a2, a3
+; ZVFH-NEXT: .LBB85_2:
+; ZVFH-NEXT: vsetvli zero, a2, e16, m8, ta, ma
+; ZVFH-NEXT: vmv1r.v v0, v24
+; ZVFH-NEXT: csrr a0, vlenb
+; ZVFH-NEXT: slli a0, a0, 3
+; ZVFH-NEXT: add a0, sp, a0
+; ZVFH-NEXT: addi a0, a0, 16
+; ZVFH-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
+; ZVFH-NEXT: addi a0, sp, 16
+; ZVFH-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
+; ZVFH-NEXT: vmfeq.vv v16, v8, v24, v0.t
+; ZVFH-NEXT: add a0, a1, a1
+; ZVFH-NEXT: vsetvli zero, a0, e8, m1, tu, ma
+; ZVFH-NEXT: vslideup.vx v16, v1, a1
+; ZVFH-NEXT: vmv1r.v v0, v16
+; ZVFH-NEXT: csrr a0, vlenb
+; ZVFH-NEXT: slli a0, a0, 4
+; ZVFH-NEXT: add sp, sp, a0
+; ZVFH-NEXT: addi sp, sp, 16
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vv_nxv64f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: addi sp, sp, -16
+; ZVFHMIN-NEXT: .cfi_def_cfa_offset 16
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: li a3, 34
+; ZVFHMIN-NEXT: mul a1, a1, a3
+; ZVFHMIN-NEXT: sub sp, sp, a1
+; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x22, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 34 * vlenb
+; ZVFHMIN-NEXT: vmv8r.v v24, v16
+; ZVFHMIN-NEXT: csrr a1, vlenb
+; ZVFHMIN-NEXT: li a3, 18
+; ZVFHMIN-NEXT: mul a1, a1, a3
+; ZVFHMIN-NEXT: add a1, sp, a1
+; ZVFHMIN-NEXT: addi a1, a1, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m1, ta, ma
+; ZVFHMIN-NEXT: slli a1, a3, 3
+; ZVFHMIN-NEXT: add a1, a0, a1
+; ZVFHMIN-NEXT: vl8re16.v v16, (a1)
+; ZVFHMIN-NEXT: slli a5, a3, 2
+; ZVFHMIN-NEXT: sub a1, a2, a5
+; ZVFHMIN-NEXT: sltu a4, a2, a1
+; ZVFHMIN-NEXT: addi a4, a4, -1
+; ZVFHMIN-NEXT: and a6, a4, a1
+; ZVFHMIN-NEXT: slli a4, a3, 1
+; ZVFHMIN-NEXT: sub a1, a6, a4
+; ZVFHMIN-NEXT: sltu a7, a6, a1
+; ZVFHMIN-NEXT: addi a7, a7, -1
+; ZVFHMIN-NEXT: and a7, a7, a1
+; ZVFHMIN-NEXT: srli a1, a3, 1
+; ZVFHMIN-NEXT: csrr t0, vlenb
+; ZVFHMIN-NEXT: add t0, sp, t0
+; ZVFHMIN-NEXT: addi t0, t0, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (t0) # Unknown-size Folded Spill
+; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a1
+; ZVFHMIN-NEXT: srli a3, a3, 2
+; ZVFHMIN-NEXT: vl8re16.v v8, (a0)
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: li t0, 26
+; ZVFHMIN-NEXT: mul a0, a0, t0
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
+; ZVFHMIN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vs1r.v v0, (a0) # Unknown-size Folded Spill
+; ZVFHMIN-NEXT: vslidedown.vx v0, v0, a3
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20
+; ZVFHMIN-NEXT: vmv4r.v v16, v24
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: li t0, 10
+; ZVFHMIN-NEXT: mul a0, a0, t0
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v28
+; ZVFHMIN-NEXT: vsetvli zero, a7, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v26, v16, v8, v0.t
+; ZVFHMIN-NEXT: bltu a6, a4, .LBB85_2
+; ZVFHMIN-NEXT: # %bb.1:
+; ZVFHMIN-NEXT: mv a6, a4
+; ZVFHMIN-NEXT: .LBB85_2:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: slli a0, a0, 1
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v16
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: li a7, 10
+; ZVFHMIN-NEXT: mul a0, a0, a7
+; ZVFHMIN-NEXT: add a0, sp, a0
+; ZVFHMIN-NEXT: addi a0, a0, 16
+; ZVFHMIN-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v0
+; ZVFHMIN-NEXT: vsetvli zero, a6, e32, m8, ta, ma
+; ZVFHMIN-NEXT: addi a0, sp, 16
+; ZVFHMIN-NEXT: vl1r.v v0, (a0) # Unknown-size Folded Reload
+; ZVFHMIN-NEXT: vmfeq.vv v2, v16, v8, v0.t
+; ZVFHMIN-NEXT: add a0, a3, a3
+; ZVFHMIN-NEXT: bltu a2, a5, .LBB85_4
+; ZVFHMIN-NEXT: # %bb.3:
+; ZVFHMIN-NEXT: mv a2, a5
+; ZVFHMIN-NEXT: .LBB85_4:
+; ZVFHMIN-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
+; ZVFHMIN-NEXT: vslideup.vx v2, v26, a3
+; ZVFHMIN-NEXT: sub a5, a2, a4
+; ZVFHMIN-NEXT: sltu a6, a2, a5
+; ZVFHMIN-NEXT: addi a6, a6, -1
+; ZVFHMIN-NEXT: and a5, a6, a5
+; ZVFHMIN-NEXT: vsetvli a6, zero, e8, mf2, ta, ma
+; ZVFHMIN-NEXT: csrr a6, vlenb
+; ZVFHMIN-NEXT: add a6, sp, a6
+; ZVFHMIN-NEXT: addi a6, a6, 16
+; ZVFHMIN-NEXT: vl1r.v v8, (a6) # Unknown-size Folded Reload
+; ZVFHMIN-NEXT: vmv1r.v v1, v8
+; ZVFHMIN-NEXT: vslidedown.vx v0, v8, a3
+; ZVFHMIN-NEXT: vsetvli a6, zero, e16, m4, ta, ma
+; ZVFHMIN-NEXT: csrr a6, vlenb
+; ZVFHMIN-NEXT: li a7, 18
+; ZVFHMIN-NEXT: mul a6, a6, a7
+; ZVFHMIN-NEXT: add a6, sp, a6
+; ZVFHMIN-NEXT: addi a6, a6, 16
+; ZVFHMIN-NEXT: vl8r.v v24, (a6) # Unknown-size Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v28
+; ZVFHMIN-NEXT: csrr a6, vlenb
+; ZVFHMIN-NEXT: li a7, 10
+; ZVFHMIN-NEXT: mul a6, a6, a7
+; ZVFHMIN-NEXT: add a6, sp, a6
+; ZVFHMIN-NEXT: addi a6, a6, 16
+; ZVFHMIN-NEXT: vs8r.v v8, (a6) # Unknown-size Folded Spill
+; ZVFHMIN-NEXT: csrr a6, vlenb
+; ZVFHMIN-NEXT: li a7, 26
+; ZVFHMIN-NEXT: mul a6, a6, a7
+; ZVFHMIN-NEXT: add a6, sp, a6
+; ZVFHMIN-NEXT: addi a6, a6, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a6) # Unknown-size Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v20
+; ZVFHMIN-NEXT: vsetvli zero, a5, e32, m8, ta, ma
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: li a6, 10
+; ZVFHMIN-NEXT: mul a5, a5, a6
+; ZVFHMIN-NEXT: add a5, sp, a5
+; ZVFHMIN-NEXT: addi a5, a5, 16
+; ZVFHMIN-NEXT: vl8r.v v16, (a5) # Unknown-size Folded Reload
+; ZVFHMIN-NEXT: vmfeq.vv v3, v16, v8, v0.t
+; ZVFHMIN-NEXT: bltu a2, a4, .LBB85_6
+; ZVFHMIN-NEXT: # %bb.5:
+; ZVFHMIN-NEXT: mv a2, a4
+; ZVFHMIN-NEXT: .LBB85_6:
+; ZVFHMIN-NEXT: vsetvli a4, zero, e16, m4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
+; ZVFHMIN-NEXT: csrr a4, vlenb
+; ZVFHMIN-NEXT: li a5, 26
+; ZVFHMIN-NEXT: mul a4, a4, a5
+; ZVFHMIN-NEXT: add a4, sp, a4
+; ZVFHMIN-NEXT: addi a4, a4, 16
+; ZVFHMIN-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
+; ZVFHMIN-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; ZVFHMIN-NEXT: vmv1r.v v0, v1
+; ZVFHMIN-NEXT: vmfeq.vv v8, v16, v24, v0.t
+; ZVFHMIN-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
+; ZVFHMIN-NEXT: vslideup.vx v8, v3, a3
+; ZVFHMIN-NEXT: add a0, a1, a1
+; ZVFHMIN-NEXT: vsetvli zero, a0, e8, m1, tu, ma
+; ZVFHMIN-NEXT: vslideup.vx v8, v2, a1
+; ZVFHMIN-NEXT: vmv1r.v v0, v8
+; ZVFHMIN-NEXT: csrr a0, vlenb
+; ZVFHMIN-NEXT: li a1, 34
+; ZVFHMIN-NEXT: mul a0, a0, a1
+; ZVFHMIN-NEXT: add sp, sp, a0
+; ZVFHMIN-NEXT: addi sp, sp, 16
+; ZVFHMIN-NEXT: ret
%v = call <vscale x 64 x i1> @llvm.vp.fcmp.nxv64f16(<vscale x 64 x half> %va, <vscale x 64 x half> %vb, metadata !"oeq", <vscale x 64 x i1> %m, i32 %evl)
ret <vscale x 64 x i1> %v
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll b/llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
index baa3d0645a989a6..e77966d8c43b37b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/setcc-fp.ll
@@ -1,28 +1,54 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=ilp32d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV32
; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=lp64d \
-; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,RV64
+; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN32
+; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfhmin,+v -target-abi=lp64d \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN64
; FIXME: The scalar/vector operations ('fv' tests) should swap operands and
; condition codes accordingly in order to generate a 'vf' instruction.
define <vscale x 8 x i1> @fcmp_oeq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_oeq_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfeq.vv v0, v8, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfeq.vv v0, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp oeq <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_oeq_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfeq.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v16
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oeq <vscale x 8 x half> %va, %splat
@@ -30,11 +56,24 @@ define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_oeq_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_oeq_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_fv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfeq.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_fv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oeq <vscale x 8 x half> %splat, %va
@@ -42,21 +81,43 @@ define <vscale x 8 x i1> @fcmp_oeq_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_oeq_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_oeq_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfeq.vv v0, v8, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vv_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfeq.vv v0, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vv_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp oeq <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_oeq_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oeq_vf_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfeq.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oeq_vf_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v16
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oeq <vscale x 8 x half> %va, %splat
@@ -64,21 +125,43 @@ define <vscale x 8 x i1> @fcmp_oeq_vf_nxv8f16_nonans(<vscale x 8 x half> %va, ha
}
define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_ogt_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vv v0, v10, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ogt_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vv v0, v10, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ogt_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp ogt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ogt_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ogt_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfgt.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ogt_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ogt <vscale x 8 x half> %va, %splat
@@ -86,11 +169,24 @@ define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_ogt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ogt_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ogt_fv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ogt_fv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v12, v16
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ogt <vscale x 8 x half> %splat, %va
@@ -98,21 +194,43 @@ define <vscale x 8 x i1> @fcmp_ogt_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_ogt_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_ogt_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vv v0, v10, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ogt_vv_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vv v0, v10, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ogt_vv_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp ogt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_ogt_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ogt_vf_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfgt.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ogt_vf_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ogt <vscale x 8 x half> %va, %splat
@@ -120,21 +238,43 @@ define <vscale x 8 x i1> @fcmp_ogt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, ha
}
define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_oge_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vv v0, v10, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oge_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vv v0, v10, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oge_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp oge <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_oge_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oge_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfge.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oge_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oge <vscale x 8 x half> %va, %splat
@@ -142,11 +282,24 @@ define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_oge_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_oge_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oge_fv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oge_fv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v12, v16
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oge <vscale x 8 x half> %splat, %va
@@ -154,21 +307,43 @@ define <vscale x 8 x i1> @fcmp_oge_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_oge_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_oge_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vv v0, v10, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oge_vv_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vv v0, v10, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oge_vv_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp oge <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_oge_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_oge_vf_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfge.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_oge_vf_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp oge <vscale x 8 x half> %va, %splat
@@ -176,21 +351,43 @@ define <vscale x 8 x i1> @fcmp_oge_vf_nxv8f16_nonans(<vscale x 8 x half> %va, ha
}
define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_olt_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vv v0, v8, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vv v0, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp olt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_olt_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v12, v16
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp olt <vscale x 8 x half> %va, %splat
@@ -198,11 +395,24 @@ define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_olt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_olt_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_fv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfgt.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_fv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp olt <vscale x 8 x half> %splat, %va
@@ -210,21 +420,43 @@ define <vscale x 8 x i1> @fcmp_olt_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_olt_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_olt_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vv v0, v8, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_vv_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vv v0, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_vv_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp olt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_olt_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_olt_vf_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_olt_vf_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v12, v16
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp olt <vscale x 8 x half> %va, %splat
@@ -232,21 +464,43 @@ define <vscale x 8 x i1> @fcmp_olt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, ha
}
define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_ole_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vv v0, v8, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ole_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vv v0, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ole_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp ole <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ole_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ole_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ole_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v12, v16
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ole <vscale x 8 x half> %va, %splat
@@ -254,11 +508,24 @@ define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_ole_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ole_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ole_fv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfge.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ole_fv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ole <vscale x 8 x half> %splat, %va
@@ -266,21 +533,43 @@ define <vscale x 8 x i1> @fcmp_ole_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_ole_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_ole_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vv v0, v8, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ole_vv_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vv v0, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ole_vv_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp ole <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_ole_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ole_vf_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ole_vf_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v12, v16
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ole <vscale x 8 x half> %va, %splat
@@ -288,25 +577,51 @@ define <vscale x 8 x i1> @fcmp_ole_vf_nxv8f16_nonans(<vscale x 8 x half> %va, ha
}
define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_one_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vv v12, v8, v10
-; CHECK-NEXT: vmflt.vv v13, v10, v8
-; CHECK-NEXT: vmor.mm v0, v13, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_one_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vv v12, v8, v10
+; ZVFH-NEXT: vmflt.vv v13, v10, v8
+; ZVFH-NEXT: vmor.mm v0, v13, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_one_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12
+; ZVFHMIN-NEXT: vmflt.vv v9, v12, v16
+; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%vc = fcmp one <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_one_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vf v10, v8, fa0
-; CHECK-NEXT: vmfgt.vf v11, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v11, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_one_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vf v10, v8, fa0
+; ZVFH-NEXT: vmfgt.vf v11, v8, fa0
+; ZVFH-NEXT: vmor.mm v0, v11, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_one_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16
+; ZVFHMIN-NEXT: vmflt.vv v9, v16, v12
+; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x half> %va, %splat
@@ -314,13 +629,28 @@ define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_one_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_one_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0
-; CHECK-NEXT: vmflt.vf v11, v8, fa0
-; CHECK-NEXT: vmor.mm v0, v11, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_one_fv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfgt.vf v10, v8, fa0
+; ZVFH-NEXT: vmflt.vf v11, v8, fa0
+; ZVFH-NEXT: vmor.mm v0, v11, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_one_fv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12
+; ZVFHMIN-NEXT: vmflt.vv v9, v12, v16
+; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x half> %splat, %va
@@ -328,21 +658,43 @@ define <vscale x 8 x i1> @fcmp_one_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_one_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfne.vv v0, v8, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_one_vv_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfne.vv v0, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_one_vv_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp one <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_one_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_one_vf_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfne.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_one_vf_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v0, v12, v16
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x half> %va, %splat
@@ -350,26 +702,56 @@ define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16_nonans(<vscale x 8 x half> %va, ha
}
define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_ord_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfeq.vv v12, v10, v10
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
-; CHECK-NEXT: vmand.mm v0, v10, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ord_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfeq.vv v12, v10, v10
+; ZVFH-NEXT: vmfeq.vv v10, v8, v8
+; ZVFH-NEXT: vmand.mm v0, v10, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ord_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v10, v12, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12
+; ZVFHMIN-NEXT: vmand.mm v0, v8, v10
+; ZVFHMIN-NEXT: ret
%vc = fcmp ord <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ord_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfmv.v.f v10, fa0
-; CHECK-NEXT: vmfeq.vf v12, v10, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
-; CHECK-NEXT: vmand.mm v0, v10, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ord_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vfmv.v.f v10, fa0
+; ZVFH-NEXT: vmfeq.vf v12, v10, fa0
+; ZVFH-NEXT: vmfeq.vv v10, v8, v8
+; ZVFH-NEXT: vmand.mm v0, v10, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ord_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v9, v12, v12
+; ZVFHMIN-NEXT: vmand.mm v0, v8, v9
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ord <vscale x 8 x half> %va, %splat
@@ -377,14 +759,31 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_ord_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ord_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfmv.v.f v10, fa0
-; CHECK-NEXT: vmfeq.vf v12, v10, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
-; CHECK-NEXT: vmand.mm v0, v12, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ord_fv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vfmv.v.f v10, fa0
+; ZVFH-NEXT: vmfeq.vf v12, v10, fa0
+; ZVFH-NEXT: vmfeq.vv v10, v8, v8
+; ZVFH-NEXT: vmand.mm v0, v12, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ord_fv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v9, v12, v12
+; ZVFHMIN-NEXT: vmand.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ord <vscale x 8 x half> %splat, %va
@@ -392,26 +791,56 @@ define <vscale x 8 x i1> @fcmp_ord_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_ord_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_ord_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfeq.vv v12, v10, v10
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
-; CHECK-NEXT: vmand.mm v0, v10, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ord_vv_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfeq.vv v12, v10, v10
+; ZVFH-NEXT: vmfeq.vv v10, v8, v8
+; ZVFH-NEXT: vmand.mm v0, v10, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ord_vv_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v10, v12, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12
+; ZVFHMIN-NEXT: vmand.mm v0, v8, v10
+; ZVFHMIN-NEXT: ret
%vc = fcmp ord <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_ord_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfmv.v.f v10, fa0
-; CHECK-NEXT: vmfeq.vf v12, v10, fa0
-; CHECK-NEXT: vmfeq.vv v10, v8, v8
-; CHECK-NEXT: vmand.mm v0, v10, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ord_vf_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vfmv.v.f v10, fa0
+; ZVFH-NEXT: vmfeq.vf v12, v10, fa0
+; ZVFH-NEXT: vmfeq.vv v10, v8, v8
+; ZVFH-NEXT: vmand.mm v0, v10, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ord_vf_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v8, v12, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v9, v12, v12
+; ZVFHMIN-NEXT: vmand.mm v0, v8, v9
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ord <vscale x 8 x half> %va, %splat
@@ -419,25 +848,51 @@ define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16_nonans(<vscale x 8 x half> %va, ha
}
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_ueq_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vv v12, v8, v10
-; CHECK-NEXT: vmflt.vv v13, v10, v8
-; CHECK-NEXT: vmnor.mm v0, v13, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ueq_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vv v12, v8, v10
+; ZVFH-NEXT: vmflt.vv v13, v10, v8
+; ZVFH-NEXT: vmnor.mm v0, v13, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ueq_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12
+; ZVFHMIN-NEXT: vmflt.vv v9, v12, v16
+; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%vc = fcmp ueq <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ueq_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vf v10, v8, fa0
-; CHECK-NEXT: vmfgt.vf v11, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v11, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ueq_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vf v10, v8, fa0
+; ZVFH-NEXT: vmfgt.vf v11, v8, fa0
+; ZVFH-NEXT: vmnor.mm v0, v11, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ueq_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16
+; ZVFHMIN-NEXT: vmflt.vv v9, v16, v12
+; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x half> %va, %splat
@@ -445,13 +900,28 @@ define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ueq_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0
-; CHECK-NEXT: vmflt.vf v11, v8, fa0
-; CHECK-NEXT: vmnor.mm v0, v11, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ueq_fv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfgt.vf v10, v8, fa0
+; ZVFH-NEXT: vmflt.vf v11, v8, fa0
+; ZVFH-NEXT: vmnor.mm v0, v11, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ueq_fv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12
+; ZVFHMIN-NEXT: vmflt.vv v9, v12, v16
+; ZVFHMIN-NEXT: vmnor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x half> %splat, %va
@@ -459,21 +929,43 @@ define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_ueq_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfeq.vv v0, v8, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ueq_vv_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfeq.vv v0, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ueq_vv_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp ueq <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_ueq_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfeq.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ueq_vf_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfeq.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ueq_vf_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfeq.vv v0, v12, v16
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x half> %va, %splat
@@ -481,23 +973,47 @@ define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16_nonans(<vscale x 8 x half> %va, ha
}
define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_ugt_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vv v12, v8, v10
-; CHECK-NEXT: vmnot.m v0, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vv v12, v8, v10
+; ZVFH-NEXT: vmnot.m v0, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ugt_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%vc = fcmp ugt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ugt_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vf v10, v8, fa0
-; CHECK-NEXT: vmnot.m v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vf v10, v8, fa0
+; ZVFH-NEXT: vmnot.m v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ugt_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v12, v16
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ugt <vscale x 8 x half> %va, %splat
@@ -505,12 +1021,26 @@ define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ugt_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfge.vf v10, v8, fa0
-; CHECK-NEXT: vmnot.m v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_fv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfge.vf v10, v8, fa0
+; ZVFH-NEXT: vmnot.m v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ugt_fv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ugt <vscale x 8 x half> %splat, %va
@@ -518,21 +1048,43 @@ define <vscale x 8 x i1> @fcmp_ugt_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_ugt_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_ugt_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vv v0, v10, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_vv_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vv v0, v10, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ugt_vv_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp ugt <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_ugt_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfgt.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ugt_vf_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfgt.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ugt_vf_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ugt <vscale x 8 x half> %va, %splat
@@ -540,23 +1092,47 @@ define <vscale x 8 x i1> @fcmp_ugt_vf_nxv8f16_nonans(<vscale x 8 x half> %va, ha
}
define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_uge_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vv v12, v8, v10
-; CHECK-NEXT: vmnot.m v0, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uge_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vv v12, v8, v10
+; ZVFH-NEXT: vmnot.m v0, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uge_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%vc = fcmp uge <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_uge_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vf v10, v8, fa0
-; CHECK-NEXT: vmnot.m v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uge_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vf v10, v8, fa0
+; ZVFH-NEXT: vmnot.m v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uge_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uge <vscale x 8 x half> %va, %splat
@@ -564,12 +1140,26 @@ define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_uge_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0
-; CHECK-NEXT: vmnot.m v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uge_fv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfgt.vf v10, v8, fa0
+; ZVFH-NEXT: vmnot.m v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uge_fv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uge <vscale x 8 x half> %splat, %va
@@ -577,21 +1167,43 @@ define <vscale x 8 x i1> @fcmp_uge_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_uge_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_uge_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vv v0, v10, v8
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uge_vv_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vv v0, v10, v8
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uge_vv_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp uge <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_uge_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfge.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uge_vf_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfge.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uge_vf_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uge <vscale x 8 x half> %va, %splat
@@ -599,23 +1211,47 @@ define <vscale x 8 x i1> @fcmp_uge_vf_nxv8f16_nonans(<vscale x 8 x half> %va, ha
}
define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_ult_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vv v12, v10, v8
-; CHECK-NEXT: vmnot.m v0, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ult_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vv v12, v10, v8
+; ZVFH-NEXT: vmnot.m v0, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ult_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%vc = fcmp ult <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ult_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfge.vf v10, v8, fa0
-; CHECK-NEXT: vmnot.m v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ult_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfge.vf v10, v8, fa0
+; ZVFH-NEXT: vmnot.m v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ult_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v16, v12
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ult <vscale x 8 x half> %va, %splat
@@ -623,12 +1259,26 @@ define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ult_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vf v10, v8, fa0
-; CHECK-NEXT: vmnot.m v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ult_fv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vf v10, v8, fa0
+; ZVFH-NEXT: vmnot.m v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ult_fv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v8, v12, v16
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ult <vscale x 8 x half> %splat, %va
@@ -636,21 +1286,43 @@ define <vscale x 8 x i1> @fcmp_ult_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_ult_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_ult_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vv v0, v8, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ult_vv_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vv v0, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ult_vv_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp ult <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_ult_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ult_vf_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ult_vf_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v0, v12, v16
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ult <vscale x 8 x half> %va, %splat
@@ -658,23 +1330,47 @@ define <vscale x 8 x i1> @fcmp_ult_vf_nxv8f16_nonans(<vscale x 8 x half> %va, ha
}
define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_ule_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vv v12, v10, v8
-; CHECK-NEXT: vmnot.m v0, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vv v12, v10, v8
+; ZVFH-NEXT: vmnot.m v0, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%vc = fcmp ule <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ule_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfgt.vf v10, v8, fa0
-; CHECK-NEXT: vmnot.m v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfgt.vf v10, v8, fa0
+; ZVFH-NEXT: vmnot.m v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v16, v12
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ule <vscale x 8 x half> %va, %splat
@@ -682,12 +1378,26 @@ define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_ule_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmflt.vf v10, v8, fa0
-; CHECK-NEXT: vmnot.m v0, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_fv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmflt.vf v10, v8, fa0
+; ZVFH-NEXT: vmnot.m v0, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_fv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmflt.vv v8, v12, v16
+; ZVFHMIN-NEXT: vmnot.m v0, v8
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ule <vscale x 8 x half> %splat, %va
@@ -695,21 +1405,43 @@ define <vscale x 8 x i1> @fcmp_ule_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_ule_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_ule_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vv v0, v8, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_vv_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vv v0, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_vv_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp ule <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_ule_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfle.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_ule_vf_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfle.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_ule_vf_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfle.vv v0, v12, v16
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ule <vscale x 8 x half> %va, %splat
@@ -717,21 +1449,43 @@ define <vscale x 8 x i1> @fcmp_ule_vf_nxv8f16_nonans(<vscale x 8 x half> %va, ha
}
define <vscale x 8 x i1> @fcmp_une_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_une_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfne.vv v0, v8, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_une_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfne.vv v0, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_une_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp une <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_une_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_une_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfne.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_une_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v0, v12, v16
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp une <vscale x 8 x half> %va, %splat
@@ -739,11 +1493,24 @@ define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_une_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_une_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_une_fv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfne.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_une_fv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp une <vscale x 8 x half> %splat, %va
@@ -751,21 +1518,43 @@ define <vscale x 8 x i1> @fcmp_une_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_une_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_une_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfne.vv v0, v8, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_une_vv_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfne.vv v0, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_une_vv_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v0, v16, v12
+; ZVFHMIN-NEXT: ret
%vc = fcmp une <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_une_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfne.vf v0, v8, fa0
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_une_vf_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfne.vf v0, v8, fa0
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_une_vf_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v0, v12, v16
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp une <vscale x 8 x half> %va, %splat
@@ -773,26 +1562,56 @@ define <vscale x 8 x i1> @fcmp_une_vf_nxv8f16_nonans(<vscale x 8 x half> %va, ha
}
define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
-; CHECK-LABEL: fcmp_uno_vv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfne.vv v12, v10, v10
-; CHECK-NEXT: vmfne.vv v10, v8, v8
-; CHECK-NEXT: vmor.mm v0, v10, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uno_vv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfne.vv v12, v10, v10
+; ZVFH-NEXT: vmfne.vv v10, v8, v8
+; ZVFH-NEXT: vmor.mm v0, v10, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uno_vv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v10, v12, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12
+; ZVFHMIN-NEXT: vmor.mm v0, v8, v10
+; ZVFHMIN-NEXT: ret
%vc = fcmp uno <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_uno_vf_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfmv.v.f v10, fa0
-; CHECK-NEXT: vmfne.vf v12, v10, fa0
-; CHECK-NEXT: vmfne.vv v10, v8, v8
-; CHECK-NEXT: vmor.mm v0, v10, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uno_vf_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vfmv.v.f v10, fa0
+; ZVFH-NEXT: vmfne.vf v12, v10, fa0
+; ZVFH-NEXT: vmfne.vv v10, v8, v8
+; ZVFH-NEXT: vmor.mm v0, v10, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uno_vf_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v9, v12, v12
+; ZVFHMIN-NEXT: vmor.mm v0, v8, v9
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uno <vscale x 8 x half> %va, %splat
@@ -800,14 +1619,31 @@ define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_uno_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
-; CHECK-LABEL: fcmp_uno_fv_nxv8f16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfmv.v.f v10, fa0
-; CHECK-NEXT: vmfne.vf v12, v10, fa0
-; CHECK-NEXT: vmfne.vv v10, v8, v8
-; CHECK-NEXT: vmor.mm v0, v12, v10
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uno_fv_nxv8f16:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vfmv.v.f v10, fa0
+; ZVFH-NEXT: vmfne.vf v12, v10, fa0
+; ZVFH-NEXT: vmfne.vv v10, v8, v8
+; ZVFH-NEXT: vmor.mm v0, v12, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uno_fv_nxv8f16:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v9, v12, v12
+; ZVFHMIN-NEXT: vmor.mm v0, v9, v8
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uno <vscale x 8 x half> %splat, %va
@@ -815,26 +1651,56 @@ define <vscale x 8 x i1> @fcmp_uno_fv_nxv8f16(<vscale x 8 x half> %va, half %b)
}
define <vscale x 8 x i1> @fcmp_uno_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
-; CHECK-LABEL: fcmp_uno_vv_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmfne.vv v12, v10, v10
-; CHECK-NEXT: vmfne.vv v10, v8, v8
-; CHECK-NEXT: vmor.mm v0, v10, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uno_vv_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vmfne.vv v12, v10, v10
+; ZVFH-NEXT: vmfne.vv v10, v8, v8
+; ZVFH-NEXT: vmor.mm v0, v10, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uno_vv_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v10, v12, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12
+; ZVFHMIN-NEXT: vmor.mm v0, v8, v10
+; ZVFHMIN-NEXT: ret
%vc = fcmp uno <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc
}
define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16_nonans(<vscale x 8 x half> %va, half %b) #0 {
-; CHECK-LABEL: fcmp_uno_vf_nxv8f16_nonans:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vfmv.v.f v10, fa0
-; CHECK-NEXT: vmfne.vf v12, v10, fa0
-; CHECK-NEXT: vmfne.vv v10, v8, v8
-; CHECK-NEXT: vmor.mm v0, v10, v12
-; CHECK-NEXT: ret
+; ZVFH-LABEL: fcmp_uno_vf_nxv8f16_nonans:
+; ZVFH: # %bb.0:
+; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; ZVFH-NEXT: vfmv.v.f v10, fa0
+; ZVFH-NEXT: vmfne.vf v12, v10, fa0
+; ZVFH-NEXT: vmfne.vv v10, v8, v8
+; ZVFH-NEXT: vmor.mm v0, v10, v12
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fcmp_uno_vf_nxv8f16_nonans:
+; ZVFHMIN: # %bb.0:
+; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0
+; ZVFHMIN-NEXT: vsetvli a0, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmv.v.f v12, fa5
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v10, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v8, v12, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vmfne.vv v9, v12, v12
+; ZVFHMIN-NEXT: vmor.mm v0, v8, v9
+; ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%vc = fcmp uno <vscale x 8 x half> %va, %splat
@@ -2537,6 +3403,32 @@ define <vscale x 16 x i1> @fcmp_oeq_vf_nx16f64(<vscale x 16 x double> %va) {
; RV64-NEXT: vsetvli zero, a1, e8, mf4, tu, ma
; RV64-NEXT: vslideup.vx v0, v24, a0
; RV64-NEXT: ret
+;
+; ZVFHMIN32-LABEL: fcmp_oeq_vf_nx16f64:
+; ZVFHMIN32: # %bb.0:
+; ZVFHMIN32-NEXT: fcvt.d.w fa5, zero
+; ZVFHMIN32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; ZVFHMIN32-NEXT: vmfeq.vf v24, v16, fa5
+; ZVFHMIN32-NEXT: vmfeq.vf v0, v8, fa5
+; ZVFHMIN32-NEXT: csrr a0, vlenb
+; ZVFHMIN32-NEXT: srli a0, a0, 3
+; ZVFHMIN32-NEXT: add a1, a0, a0
+; ZVFHMIN32-NEXT: vsetvli zero, a1, e8, mf4, tu, ma
+; ZVFHMIN32-NEXT: vslideup.vx v0, v24, a0
+; ZVFHMIN32-NEXT: ret
+;
+; ZVFHMIN64-LABEL: fcmp_oeq_vf_nx16f64:
+; ZVFHMIN64: # %bb.0:
+; ZVFHMIN64-NEXT: fmv.d.x fa5, zero
+; ZVFHMIN64-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; ZVFHMIN64-NEXT: vmfeq.vf v24, v16, fa5
+; ZVFHMIN64-NEXT: vmfeq.vf v0, v8, fa5
+; ZVFHMIN64-NEXT: csrr a0, vlenb
+; ZVFHMIN64-NEXT: srli a0, a0, 3
+; ZVFHMIN64-NEXT: add a1, a0, a0
+; ZVFHMIN64-NEXT: vsetvli zero, a1, e8, mf4, tu, ma
+; ZVFHMIN64-NEXT: vslideup.vx v0, v24, a0
+; ZVFHMIN64-NEXT: ret
%vc = fcmp oeq <vscale x 16 x double> %va, zeroinitializer
ret <vscale x 16 x i1> %vc
}
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