[llvm] [RISCV] Fix bad isel predicate handling for Ztso. (PR #66739)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 18 22:47:16 PDT 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
<details>
<summary>Changes</summary>
The predicates inside the AMOPat class were being overridden by the Predicates = [HasStdExtA] at the instantiation.
---
Patch is 162.06 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/66739.diff
3 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+1-1)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoA.td (+2-2)
- (modified) llvm/test/CodeGen/RISCV/atomic-rmw.ll (+2501-1173)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 6381263b37613b3..5231f3c3cf3df2d 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -549,7 +549,7 @@ def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,
def FeatureStdExtZtso
: SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
"'Ztso' (Memory Model - Total Store Order)">;
-def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZTso()">,
+def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZtso()">,
AssemblerPredicate<(all_of FeatureStdExtZtso),
"'Ztso' (Memory Model - Total Store Order)">;
def NotHasStdExtZtso : Predicate<"!Subtarget->hasStdExtZtso()">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
index d7314866789ce47..5d4fb31d967b931 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
@@ -156,8 +156,6 @@ let Predicates = [HasStdExtA, HasStdExtZtso] in {
}
}
-let Predicates = [HasStdExtA] in {
-
defm : AMOPat<"atomic_swap_32", "AMOSWAP_W">;
defm : AMOPat<"atomic_load_add_32", "AMOADD_W">;
defm : AMOPat<"atomic_load_and_32", "AMOAND_W">;
@@ -168,6 +166,8 @@ defm : AMOPat<"atomic_load_min_32", "AMOMIN_W">;
defm : AMOPat<"atomic_load_umax_32", "AMOMAXU_W">;
defm : AMOPat<"atomic_load_umin_32", "AMOMINU_W">;
+let Predicates = [HasStdExtA] in {
+
/// Pseudo AMOs
class PseudoAMO : Pseudo<(outs GPR:$res, GPR:$scratch),
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
index c47d4484d8c0d80..53702403879c758 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
@@ -515,16 +515,27 @@ define i8 @atomicrmw_xchg_0_i8_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_0_i8_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a2, 255
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: not a2, a2
-; RV32IA-NEXT: amoand.w.aq a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a2, 255
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: not a2, a2
+; RV32IA-WMO-NEXT: amoand.w.aq a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a2, 255
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: not a2, a2
+; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_0_i8_acquire:
; RV64I: # %bb.0:
@@ -537,16 +548,27 @@ define i8 @atomicrmw_xchg_0_i8_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_0_i8_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a2, 255
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: not a2, a2
-; RV64IA-NEXT: amoand.w.aq a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.aq a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 acquire
ret i8 %1
}
@@ -563,16 +585,27 @@ define i8 @atomicrmw_xchg_0_i8_release(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_0_i8_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a2, 255
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: not a2, a2
-; RV32IA-NEXT: amoand.w.rl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i8_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a2, 255
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: not a2, a2
+; RV32IA-WMO-NEXT: amoand.w.rl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i8_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a2, 255
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: not a2, a2
+; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_0_i8_release:
; RV64I: # %bb.0:
@@ -585,16 +618,27 @@ define i8 @atomicrmw_xchg_0_i8_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_0_i8_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a2, 255
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: not a2, a2
-; RV64IA-NEXT: amoand.w.rl a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.rl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 release
ret i8 %1
}
@@ -611,16 +655,27 @@ define i8 @atomicrmw_xchg_0_i8_acq_rel(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_0_i8_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a2, 255
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: not a2, a2
-; RV32IA-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a2, 255
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: not a2, a2
+; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a2, 255
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: not a2, a2
+; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_0_i8_acq_rel:
; RV64I: # %bb.0:
@@ -633,16 +688,27 @@ define i8 @atomicrmw_xchg_0_i8_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_0_i8_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a2, 255
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: not a2, a2
-; RV64IA-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 acq_rel
ret i8 %1
}
@@ -659,16 +725,27 @@ define i8 @atomicrmw_xchg_0_i8_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_0_i8_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a2, 255
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: not a2, a2
-; RV32IA-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a2, 255
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: not a2, a2
+; RV32IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a2, 255
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: not a2, a2
+; RV32IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_0_i8_seq_cst:
; RV64I: # %bb.0:
@@ -681,16 +758,27 @@ define i8 @atomicrmw_xchg_0_i8_seq_cst(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_0_i8_seq_cst:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a2, 255
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: not a2, a2
-; RV64IA-NEXT: amoand.w.aqrl a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: not a2, a2
+; RV64IA-WMO-NEXT: amoand.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_0_i8_seq_cst:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: not a2, a2
+; RV64IA-TSO-NEXT: amoand.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 0 seq_cst
ret i8 %1
}
@@ -753,15 +841,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_acquire(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a2, 255
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: amoor.w.aq a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a2, 255
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: amoor.w.aq a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a2, 255
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
; RV64I: # %bb.0:
@@ -774,15 +872,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_acquire(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a2, 255
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: amoor.w.aq a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.aq a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_acquire:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 -1 acquire
ret i8 %1
}
@@ -799,15 +907,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_release(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_minus_1_i8_release:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a2, 255
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: amoor.w.rl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a2, 255
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: amoor.w.rl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a2, 255
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_minus_1_i8_release:
; RV64I: # %bb.0:
@@ -820,15 +938,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_release(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_minus_1_i8_release:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a2, 255
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: amoor.w.rl a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.rl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_release:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 -1 release
ret i8 %1
}
@@ -845,15 +973,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_acq_rel(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a2, 255
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a2, 255
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-TSO-NEXT: andi a1, a0, -4
+; RV32IA-TSO-NEXT: slli a0, a0, 3
+; RV32IA-TSO-NEXT: li a2, 255
+; RV32IA-TSO-NEXT: sll a2, a2, a0
+; RV32IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV32IA-TSO-NEXT: srl a0, a1, a0
+; RV32IA-TSO-NEXT: ret
;
; RV64I-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
; RV64I: # %bb.0:
@@ -866,15 +1004,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_acq_rel(ptr %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; RV64IA-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
-; RV64IA: # %bb.0:
-; RV64IA-NEXT: andi a1, a0, -4
-; RV64IA-NEXT: slli a0, a0, 3
-; RV64IA-NEXT: li a2, 255
-; RV64IA-NEXT: sllw a2, a2, a0
-; RV64IA-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV64IA-NEXT: srlw a0, a1, a0
-; RV64IA-NEXT: ret
+; RV64IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV64IA-WMO: # %bb.0:
+; RV64IA-WMO-NEXT: andi a1, a0, -4
+; RV64IA-WMO-NEXT: slli a0, a0, 3
+; RV64IA-WMO-NEXT: li a2, 255
+; RV64IA-WMO-NEXT: sllw a2, a2, a0
+; RV64IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV64IA-WMO-NEXT: srlw a0, a1, a0
+; RV64IA-WMO-NEXT: ret
+;
+; RV64IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_acq_rel:
+; RV64IA-TSO: # %bb.0:
+; RV64IA-TSO-NEXT: andi a1, a0, -4
+; RV64IA-TSO-NEXT: slli a0, a0, 3
+; RV64IA-TSO-NEXT: li a2, 255
+; RV64IA-TSO-NEXT: sllw a2, a2, a0
+; RV64IA-TSO-NEXT: amoor.w a1, a2, (a1)
+; RV64IA-TSO-NEXT: srlw a0, a1, a0
+; RV64IA-TSO-NEXT: ret
%1 = atomicrmw xchg ptr %a, i8 -1 acq_rel
ret i8 %1
}
@@ -891,15 +1039,25 @@ define i8 @atomicrmw_xchg_minus_1_i8_seq_cst(ptr %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV32IA-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
-; RV32IA: # %bb.0:
-; RV32IA-NEXT: andi a1, a0, -4
-; RV32IA-NEXT: slli a0, a0, 3
-; RV32IA-NEXT: li a2, 255
-; RV32IA-NEXT: sll a2, a2, a0
-; RV32IA-NEXT: amoor.w.aqrl a1, a2, (a1)
-; RV32IA-NEXT: srl a0, a1, a0
-; RV32IA-NEXT: ret
+; RV32IA-WMO-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
+; RV32IA-WMO: # %bb.0:
+; RV32IA-WMO-NEXT: andi a1, a0, -4
+; RV32IA-WMO-NEXT: slli a0, a0, 3
+; RV32IA-WMO-NEXT: li a2, 255
+; RV32IA-WMO-NEXT: sll a2, a2, a0
+; RV32IA-WMO-NEXT: amoor.w.aqrl a1, a2, (a1)
+; RV32IA-WMO-NEXT: srl a0, a1, a0
+; RV32IA-WMO-NEXT: ret
+;
+; RV32IA-TSO-LABEL: atomicrmw_xchg_minus_1_i8_seq_cst:
+; RV32IA-TSO: # %bb.0:
+; RV32IA-...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/66739
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