[PATCH] D152828: [MachineSink][AArch64] Sink instruction copies when they can replace copy into hard register or folded into addressing mode

[Momchil Velikov via Phabricator via llvm-commits]

chill marked 2 inline comments as done.
chill added inline comments.


================
Comment at: llvm/lib/CodeGen/MachineSink.cpp:467-468
+        // don't consider that live range extended.
+        const TargetRegisterClass *RCS =
+            MRI->getRegClass(UseInst.getOperand(1).getReg());
+        if (RCA && RCA->hasSuperClassEq(RCS))
----------------
dmgreen wrote:
> Is this assuming that the UseInst is a copy or that canFoldIntoAddrMode instructions always have an Operand(1) which is a reg? Is UseInst.getOperand(1) always MO in for AArch64?
The comment is obsolete and the expression is incorrect.

We have here the original instruction
    DefReg = opc UsedRegA, UsedRegB
and a chain of copies (maybe empty)
    DefReg ->  ... -> Reg
and the instruction we're trying to fold into
   ... = opc Op0, Op1, ..., Reg, ...

We are replacing `Reg` with some expression, which involves `UsedRegA` and `UsedRegB` , so potentially where we had one register now we would have two, so register pressure may increase. 
However, if `Reg` is the in the same register class as `UsedRegA` or `UsedRegB`, then register pressure for that register class does not increase, as we are simply replacing one virtual reg with another virtual reg.

The expression should be just ` const TargetRegisterClass *RCS = MRI->getRegClass(Reg);`


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152828/new/

https://reviews.llvm.org/D152828