[llvm] [RISCV] Truncate constants to eltwidth before checking simm5 when con… (PR #67062)

[Craig Topper via llvm-commits]

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@@ -14435,7 +14435,8 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
     // patterns on rv32..
     ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Scalar);
     if (isOneConstant(VL) && EltWidth <= Subtarget.getXLen() &&
-        (!Const || Const->isZero() || !isInt<5>(Const->getSExtValue())))
+        (!Const || Const->isZero() ||
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topperc wrote:

I don't think the DemandedBits will turn a zero extended i64 constant into a sign extended i64 constant if the upper bits aren't used. Is that what you're suggesting?

https://github.com/llvm/llvm-project/pull/67062