[llvm] ISel/RISCV: remove dead code corresponding to VP_FSH[L|R] (PR #67035)

[Ramkumar Ramachandra via llvm-commits]

https://github.com/artagnon created https://github.com/llvm/llvm-project/pull/67035

70de0e ([VP][RISCV] Add vp.fshl/fshr and RISC-V support.) introduced VP_FSHL and VP_FSHR, by using a generic expansion for all targets: the core of this change is in TargetLowering. However, the commit erroneously introduced dead code in RISCVISelLowering. Remove this dead code.

>From 149c321439cfd9372e65e8eab127b8bb826a1a42 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <Ramkumar.Ramachandra at imgtec.com>
Date: Thu, 21 Sep 2023 16:55:30 +0100
Subject: [PATCH] ISel/RISCV: remove dead code corresponding to VP_FSH[L|R]

70de0e ([VP][RISCV] Add vp.fshl/fshr and RISC-V support.) introduced
VP_FSHL and VP_FSHR, by using a generic expansion for all targets: the
core of this change is in TargetLowering. However, the commit
erroneously introduced dead code in RISCVISelLowering. Remove this dead
code.
---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 --
 1 file changed, 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f1cea6c6756f4fc..9533f746305c3ae 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -715,8 +715,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
       setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, VT,
                          Legal);
 
-      setOperationAction({ISD::VP_FSHL, ISD::VP_FSHR}, VT, Expand);
-
       // Custom-lower extensions and truncations from/to mask types.
       setOperationAction({ISD::ANY_EXTEND, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND},
                          VT, Custom);