[llvm] [RISCV] Use LMUL=1 for vmv_s_x_vl with non-undef passthru (PR #66659)

[Philip Reames via llvm-commits]

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@@ -550,9 +550,9 @@ define void @insertelt_c6_v8i64_0_add(ptr %x, ptr %y) {
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    li a2, 6
-; CHECK-NEXT:    vsetvli zero, zero, e64, m4, tu, ma
+; CHECK-NEXT:    vsetivli zero, 8, e64, m1, tu, ma
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preames wrote:

Continuing from our chat offline... Ah, here's the problem I hit when I tried this before.

8 is not a valid VL for m1.  Trying to set VL=8 will result in a VL=2 on zvl126b hardware.  This is correct for the vmv.s.x, but forces two pairs of VL toggles in this bit of assembly.  (We'd previously had two VTYPE toggles, but VTYPE is cheaper than VL.)

This isn't a correctness issue, but it does raise a question of profitability.  Is it worth two VL toggles to use a narrower LMUL here?  I'm not sure it is.  

Alternatively, can we reasonably strengthen InsertVSETVLI to undo the damage here?  Maybe we should allow the m4 to slide over the vmv.s.x if doing so eliminates the VL toggle?

https://github.com/llvm/llvm-project/pull/66659