[PATCH] D159533: [DAG] getNode() - fold (zext (trunc x)) -> x iff the upper bits are known zero - add SRL support
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 24 05:50:09 PDT 2023
This revision was not accepted when it landed; it landed in state "Needs Review".
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG142efd6d6129: [AMDGPU] Add ISD::FSHR Handling to AMDGPUISD::PERM matching (authored by RKSimon).
Changed prior to commit:
https://reviews.llvm.org/D159533?vs=557246&id=557283#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D159533/new/
https://reviews.llvm.org/D159533
Files:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/test/CodeGen/AMDGPU/permute_i8.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D159533.557283.patch
Type: text/x-patch
Size: 5331 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230924/f5be169d/attachment.bin>
More information about the llvm-commits
mailing list