[llvm] 972df2c - [RISCV][GISel] Emit G_CONSTANT 0 as a copy from X0. (#67202)

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-09-22T17:04:11-07:00
New Revision: 972df2ceccbafe0cc8d1a79d08533b623a5640ab

URL: https://github.com/llvm/llvm-project/commit/972df2ceccbafe0cc8d1a79d08533b623a5640ab
DIFF: https://github.com/llvm/llvm-project/commit/972df2ceccbafe0cc8d1a79d08533b623a5640ab.diff

LOG: [RISCV][GISel] Emit G_CONSTANT 0 as a copy from X0. (#67202)

We need to use a COPY so the register coalescer can replace reads
of the register we copy to with X0. This is needed so that we use
X0 on instructions that don't have an immediate form.

This was reviewed as #67202.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
    llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant32.mir
    llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index a6163396b72d72f..4a4be79528545f8 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -228,9 +228,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
     MI.setDesc(TII.get(TargetOpcode::COPY));
     return true;
   case TargetOpcode::G_CONSTANT:
-    if (!selectConstant(MI, MIB, MRI))
-      return false;
-    break;
+    return selectConstant(MI, MIB, MRI);
   case TargetOpcode::G_BRCOND: {
     // TODO: Fold with G_ICMP.
     auto Bcc =
@@ -242,10 +240,6 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
   default:
     return false;
   }
-
-  MI.eraseFromParent();
-
-  return true;
 }
 
 void RISCVInstructionSelector::renderNegImm(MachineInstrBuilder &MIB,
@@ -312,6 +306,13 @@ bool RISCVInstructionSelector::selectConstant(MachineInstr &MI,
   Register FinalReg = MI.getOperand(0).getReg();
   int64_t Imm = MI.getOperand(1).getCImm()->getSExtValue();
 
+  if (Imm == 0) {
+    MI.getOperand(1).ChangeToRegister(RISCV::X0, false);
+    RBI.constrainGenericRegister(FinalReg, RISCV::GPRRegClass, MRI);
+    MI.setDesc(TII.get(TargetOpcode::COPY));
+    return true;
+  }
+
   RISCVMatInt::InstSeq Seq =
       RISCVMatInt::generateInstSeq(Imm, Subtarget->getFeatureBits());
   unsigned NumInsts = Seq.size();
@@ -358,6 +359,7 @@ bool RISCVInstructionSelector::selectConstant(MachineInstr &MI,
     SrcReg = DstReg;
   }
 
+  MI.eraseFromParent();
   return true;
 }
 

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
index be25efdc78d255d..c503d6541b0a577 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll
@@ -133,14 +133,12 @@ entry:
 define i32 @neg_i32(i32 %a) {
 ; RV32IM-LABEL: neg_i32:
 ; RV32IM:       # %bb.0: # %entry
-; RV32IM-NEXT:    li a1, 0
-; RV32IM-NEXT:    sub a0, a1, a0
+; RV32IM-NEXT:    neg a0, a0
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: neg_i32:
 ; RV64IM:       # %bb.0: # %entry
-; RV64IM-NEXT:    li a1, 0
-; RV64IM-NEXT:    subw a0, a1, a0
+; RV64IM-NEXT:    negw a0, a0
 ; RV64IM-NEXT:    ret
 entry:
   %0 = sub i32 0, %a
@@ -481,18 +479,16 @@ entry:
 define i64 @neg_i64(i64 %a) {
 ; RV32IM-LABEL: neg_i64:
 ; RV32IM:       # %bb.0: # %entry
-; RV32IM-NEXT:    li a3, 0
-; RV32IM-NEXT:    sub a2, a3, a0
-; RV32IM-NEXT:    sltu a0, a3, a0
-; RV32IM-NEXT:    sub a1, a3, a1
+; RV32IM-NEXT:    neg a2, a0
+; RV32IM-NEXT:    snez a0, a0
+; RV32IM-NEXT:    neg a1, a1
 ; RV32IM-NEXT:    sub a1, a1, a0
 ; RV32IM-NEXT:    mv a0, a2
 ; RV32IM-NEXT:    ret
 ;
 ; RV64IM-LABEL: neg_i64:
 ; RV64IM:       # %bb.0: # %entry
-; RV64IM-NEXT:    li a1, 0
-; RV64IM-NEXT:    sub a0, a1, a0
+; RV64IM-NEXT:    neg a0, a0
 ; RV64IM-NEXT:    ret
 entry:
   %0 = sub i64 0, %a

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant32.mir
index e1715c7a330d0ea..4af5d1c6173b44a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant32.mir
@@ -115,8 +115,8 @@ body:            |
     ; CHECK-LABEL: name: const_i32_0
     ; CHECK: liveins: $x10
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 0
-    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
+    ; CHECK-NEXT: $x10 = COPY [[COPY]]
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:gprb(s32) = G_CONSTANT i32 0
     $x10 = COPY %0(s32)

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir
index 6c6410f2f9293d6..bcd4a225a321129 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/constant64.mir
@@ -118,8 +118,8 @@ body:            |
     ; CHECK-LABEL: name: const_i64_0
     ; CHECK: liveins: $x10
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 0
-    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
+    ; CHECK-NEXT: $x10 = COPY [[COPY]]
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:gprb(s64) = G_CONSTANT i64 0
     $x10 = COPY %0(s64)
@@ -245,8 +245,8 @@ body:            |
     ; CHECK-LABEL: name: const_i32_0
     ; CHECK: liveins: $x10
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 0
-    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
+    ; CHECK-NEXT: $x10 = COPY [[COPY]]
     ; CHECK-NEXT: PseudoRET implicit $x10
     %0:gprb(s32) = G_CONSTANT i32 0
     %1:gprb(s64) = G_ANYEXT %0(s32)