[llvm] [AArch64] Allow SVE code generation for fixed-width vectors (PR #67122)

[David Sherwood via llvm-commits]

david-arm wrote:

Hi @igogo-x86, do you have any performance results for benchmarks on SVE hardware? For example, I know that we vectorise using tail-folding for neoverse-v1 and this patch will potentially make it more likely that we see fixed-width vector predicated loops. x264 is one benchmark that we know is sensitive to tail-folding and the choice of VF.

https://github.com/llvm/llvm-project/pull/67122