[llvm] d9a0163 - Revert "[NVPTX] Improve lowering of v2i16 logical ops. (#67073)"
Fangrui Song via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 22 19:24:23 PDT 2023
Author: Fangrui Song
Date: 2023-09-22T19:24:18-07:00
New Revision: d9a0163e273fa00c55090a4b813d025affce8940
URL: https://github.com/llvm/llvm-project/commit/d9a0163e273fa00c55090a4b813d025affce8940
DIFF: https://github.com/llvm/llvm-project/commit/d9a0163e273fa00c55090a4b813d025affce8940.diff
LOG: Revert "[NVPTX] Improve lowering of v2i16 logical ops. (#67073)"
This reverts commit 648579006234b7608549cf708c07aac4d6283a1f.
Caused xla/tests:float8_test_gpu to fail
```
LLVM ERROR: Cannot select: t118: v2i16 = or t375, t401
t375: v2i16 = BUILD_VECTOR t374, t372
t374: i16 = select t247, Constant:i16<8960>, t360
t247: i1 = setcc t199, Constant:i16<7>, seteq:ch
t199: i16 = extract_vector_elt t187, Constant:i64<0>
t187: v2i16 = and t183, t410
t183: v2i16 = BUILD_VECTOR t383, t384
...
```
Acked by author to revert
Added:
Modified:
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index 1388811a2d52ffc..e9401d4b93c371e 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -642,9 +642,10 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
setI16x2OperationAction(ISD::UREM, MVT::v2i16, Legal, Custom);
// Other arithmetic and logic ops are unsupported.
- setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SRA, ISD::SRL, ISD::MULHS,
- ISD::MULHU, ISD::FP_TO_SINT, ISD::FP_TO_UINT,
- ISD::SINT_TO_FP, ISD::UINT_TO_FP},
+ setOperationAction({ISD::AND, ISD::OR, ISD::XOR, ISD::SDIV, ISD::UDIV,
+ ISD::SRA, ISD::SRL, ISD::MULHS, ISD::MULHU,
+ ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::SINT_TO_FP,
+ ISD::UINT_TO_FP},
MVT::v2i16, Expand);
setOperationAction(ISD::ADDC, MVT::i32, Legal);
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 8f88b06372b245d..ad10d7938ef12e4 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -1486,17 +1486,6 @@ defm OR : BITWISE<"or", or>;
defm AND : BITWISE<"and", and>;
defm XOR : BITWISE<"xor", xor>;
-// Lower logical ops as bitwise ops on b32.
-// By this point the constants get legalized into a bitcast from i32, so that's
-// what we need to match here.
-def: Pat<(or Int32Regs:$a, (v2i16 (bitconvert (i32 imm:$b)))),
- (ORb32ri Int32Regs:$a, imm:$b)>;
-def: Pat<(xor Int32Regs:$a, (v2i16 (bitconvert (i32 imm:$b)))),
- (XORb32ri Int32Regs:$a, imm:$b)>;
-def: Pat<(and Int32Regs:$a, (v2i16 (bitconvert (i32 imm:$b)))),
- (ANDb32ri Int32Regs:$a, imm:$b)>;
-
-
def NOT1 : NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$src),
"not.pred \t$dst, $src;",
[(set Int1Regs:$dst, (not Int1Regs:$src))]>;
diff --git a/llvm/test/CodeGen/NVPTX/i16x2-instructions.ll b/llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
index d14514cb53d3a93..59d1d84b191c31b 100644
--- a/llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
@@ -235,70 +235,6 @@ define <2 x i16> @test_mul(<2 x i16> %a, <2 x i16> %b) #0 {
ret <2 x i16> %r
}
-;; Logical ops are available on all GPUs as regular 32-bit logical ops
-; COMMON-LABEL: test_or(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_or_param_0];
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_or_param_1];
-; COMMON-NEXT: or.b32 [[R:%r[0-9]+]], [[A]], [[B]];
-; COMMON-NEXT: st.param.b32 [func_retval0+0], [[R]];
-; COMMON-NEXT: ret;
-define <2 x i16> @test_or(<2 x i16> %a, <2 x i16> %b) #0 {
- %r = or <2 x i16> %a, %b
- ret <2 x i16> %r
-}
-
-; Check that we can lower or with immediate arguments.
-; COMMON-LABEL: test_or_imm_0(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_or_imm_0_param_0];
-; COMMON-NEXT: or.b32 [[R:%r[0-9]+]], [[A]], 131073;
-; COMMON-NEXT: st.param.b32 [func_retval0+0], [[R]];
-; COMMON-NEXT: ret;
-define <2 x i16> @test_or_imm_0(<2 x i16> %a) #0 {
- %r = or <2 x i16> <i16 1, i16 2>, %a
- ret <2 x i16> %r
-}
-
-; COMMON-LABEL: test_or_imm_1(
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_or_imm_1_param_0];
-; COMMON-NEXT: or.b32 [[R:%r[0-9]+]], [[A]], 131073;
-; COMMON-NEXT: st.param.b32 [func_retval0+0], [[R]];
-; COMMON-NEXT: ret;
-define <2 x i16> @test_or_imm_1(<2 x i16> %a) #0 {
- %r = or <2 x i16> %a, <i16 1, i16 2>
- ret <2 x i16> %r
-}
-
-; COMMON-LABEL: test_xor(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_xor_param_0];
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_xor_param_1];
-; COMMON-NEXT: xor.b32 [[R:%r[0-9]+]], [[A]], [[B]];
-; COMMON-NEXT: st.param.b32 [func_retval0+0], [[R]];
-; COMMON-NEXT: ret;
-define <2 x i16> @test_xor(<2 x i16> %a, <2 x i16> %b) #0 {
- %r = xor <2 x i16> %a, %b
- ret <2 x i16> %r
-}
-
-; Check that we can lower xor with immediate arguments.
-; COMMON-LABEL: test_xor_imm_0(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_xor_imm_0_param_0];
-; COMMON-NEXT: xor.b32 [[R:%r[0-9]+]], [[A]], 131073;
-; COMMON-NEXT: st.param.b32 [func_retval0+0], [[R]];
-; COMMON-NEXT: ret;
-define <2 x i16> @test_xor_imm_0(<2 x i16> %a) #0 {
- %r = xor <2 x i16> <i16 1, i16 2>, %a
- ret <2 x i16> %r
-}
-
-; COMMON-LABEL: test_xor_imm_1(
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_xor_imm_1_param_0];
-; COMMON-NEXT: xor.b32 [[R:%r[0-9]+]], [[A]], 131073;
-; COMMON-NEXT: st.param.b32 [func_retval0+0], [[R]];
-; COMMON-NEXT: ret;
-define <2 x i16> @test_xor_imm_1(<2 x i16> %a) #0 {
- %r = xor <2 x i16> %a, <i16 1, i16 2>
- ret <2 x i16> %r
-}
; COMMON-LABEL: .func test_ldst_v2i16(
; COMMON-DAG: ld.param.u64 [[A:%rd[0-9]+]], [test_ldst_v2i16_param_0];
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