[llvm] 93fde2e - [RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 19 10:02:59 PDT 2023
Author: Yingwei Zheng
Date: 2023-09-20T01:02:19+08:00
New Revision: 93fde2ea1b2cb07ed5741057571ee38e7e224978
URL: https://github.com/llvm/llvm-project/commit/93fde2ea1b2cb07ed5741057571ee38e7e224978
DIFF: https://github.com/llvm/llvm-project/commit/93fde2ea1b2cb07ed5741057571ee38e7e224978.diff
LOG: [RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
When AMOs are used to implement parallel reduction operations, typically the return value would be discarded.
This patch adds a peephole pass `RISCVDeadRegisterDefinitions`. It rewrites `rd` to `x0` when `rd` is marked as dead.
It may improve the register allocation and reduce pipeline hazards on CPUs without register renaming and OOO.
Comparison with GCC: https://godbolt.org/z/bKaxnEcec
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D158759
Added:
llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
Modified:
llvm/lib/Target/RISCV/CMakeLists.txt
llvm/lib/Target/RISCV/RISCV.h
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/test/CodeGen/RISCV/O3-pipeline.ll
llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
llvm/test/CodeGen/RISCV/branch.ll
llvm/test/CodeGen/RISCV/double-mem.ll
llvm/test/CodeGen/RISCV/float-mem.ll
llvm/test/CodeGen/RISCV/half-mem.ll
llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
llvm/test/CodeGen/RISCV/mem.ll
llvm/test/CodeGen/RISCV/mem64.ll
llvm/test/CodeGen/RISCV/rvv/localvar.ll
llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
index 6a87397862e4aec..abe2f5a6246fc25 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -27,6 +27,7 @@ add_public_tablegen_target(RISCVCommonTableGen)
add_llvm_target(RISCVCodeGen
RISCVAsmPrinter.cpp
RISCVCodeGenPrepare.cpp
+ RISCVDeadRegisterDefinitions.cpp
RISCVMakeCompressible.cpp
RISCVExpandAtomicPseudoInsts.cpp
RISCVExpandPseudoInsts.cpp
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 35c73d07a7d3c4b..702f69bcd4780a9 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -33,6 +33,9 @@ class RISCVTargetMachine;
FunctionPass *createRISCVCodeGenPreparePass();
void initializeRISCVCodeGenPreparePass(PassRegistry &);
+FunctionPass *createRISCVDeadRegisterDefinitionsPass();
+void initializeRISCVDeadRegisterDefinitionsPass(PassRegistry &);
+
FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM,
CodeGenOptLevel OptLevel);
diff --git a/llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp b/llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
new file mode 100644
index 000000000000000..7099f36dcd43c22
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
@@ -0,0 +1,106 @@
+//===- RISCVDeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+//
+// This pass rewrites Rd to x0 for instrs whose return values are unused.
+//
+//===---------------------------------------------------------------------===//
+
+#include "RISCV.h"
+#include "RISCVInstrInfo.h"
+#include "RISCVSubtarget.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+
+using namespace llvm;
+#define DEBUG_TYPE "riscv-dead-defs"
+#define RISCV_DEAD_REG_DEF_NAME "RISC-V Dead register definitions"
+
+STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
+
+namespace {
+class RISCVDeadRegisterDefinitions : public MachineFunctionPass {
+public:
+ static char ID;
+
+ RISCVDeadRegisterDefinitions() : MachineFunctionPass(ID) {
+ initializeRISCVDeadRegisterDefinitionsPass(
+ *PassRegistry::getPassRegistry());
+ }
+ bool runOnMachineFunction(MachineFunction &MF) override;
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.setPreservesCFG();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+
+ StringRef getPassName() const override { return RISCV_DEAD_REG_DEF_NAME; }
+};
+} // end anonymous namespace
+
+char RISCVDeadRegisterDefinitions::ID = 0;
+INITIALIZE_PASS(RISCVDeadRegisterDefinitions, DEBUG_TYPE,
+ RISCV_DEAD_REG_DEF_NAME, false, false)
+
+FunctionPass *llvm::createRISCVDeadRegisterDefinitionsPass() {
+ return new RISCVDeadRegisterDefinitions();
+}
+
+bool RISCVDeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
+ if (skipFunction(MF.getFunction()))
+ return false;
+
+ const MachineRegisterInfo *MRI = &MF.getRegInfo();
+ const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
+ const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
+ LLVM_DEBUG(dbgs() << "***** RISCVDeadRegisterDefinitions *****\n");
+
+ bool MadeChange = false;
+ for (MachineBasicBlock &MBB : MF) {
+ for (MachineInstr &MI : MBB) {
+ // We only handle non-computational instructions since some NOP encodings
+ // are reserved for HINT instructions.
+ const MCInstrDesc &Desc = MI.getDesc();
+ if (!Desc.mayLoad() && !Desc.mayStore() &&
+ !Desc.hasUnmodeledSideEffects())
+ continue;
+ // For PseudoVSETVLIX0, Rd = X0 has special meaning.
+ if (MI.getOpcode() == RISCV::PseudoVSETVLIX0)
+ continue;
+ for (int I = 0, E = Desc.getNumDefs(); I != E; ++I) {
+ MachineOperand &MO = MI.getOperand(I);
+ if (!MO.isReg() || !MO.isDef() || MO.isEarlyClobber())
+ continue;
+ // Be careful not to change the register if it's a tied operand.
+ if (MI.isRegTiedToUseOperand(I)) {
+ LLVM_DEBUG(dbgs() << " Ignoring, def is tied operand.\n");
+ continue;
+ }
+ // We should not have any relevant physreg defs that are replacable by
+ // zero before register allocation. So we just check for dead vreg defs.
+ Register Reg = MO.getReg();
+ if (!Reg.isVirtual() || (!MO.isDead() && !MRI->use_nodbg_empty(Reg)))
+ continue;
+ LLVM_DEBUG(dbgs() << " Dead def operand #" << I << " in:\n ";
+ MI.print(dbgs()));
+ const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF);
+ if (!(RC && RC->contains(RISCV::X0))) {
+ LLVM_DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
+ continue;
+ }
+ MO.setReg(RISCV::X0);
+ MO.setIsDead();
+ LLVM_DEBUG(dbgs() << " Replacing with zero register. New:\n ";
+ MI.print(dbgs()));
+ ++NumDeadDefsReplaced;
+ MadeChange = true;
+ }
+ }
+ }
+
+ return MadeChange;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index b42ad269c18de6f..5584fa8d503dbe4 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1592,22 +1592,6 @@ bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
for (MachineBasicBlock &MBB : MF)
doLocalPostpass(MBB);
- // Once we're fully done rewriting all the instructions, do a final pass
- // through to check for VSETVLIs which write to an unused destination.
- // For the non X0, X0 variant, we can replace the destination register
- // with X0 to reduce register pressure. This is really a generic
- // optimization which can be applied to any dead def (TODO: generalize).
- for (MachineBasicBlock &MBB : MF) {
- for (MachineInstr &MI : MBB) {
- if (MI.getOpcode() == RISCV::PseudoVSETVLI ||
- MI.getOpcode() == RISCV::PseudoVSETIVLI) {
- Register VRegDef = MI.getOperand(0).getReg();
- if (VRegDef != RISCV::X0 && MRI->use_nodbg_empty(VRegDef))
- MI.getOperand(0).setReg(RISCV::X0);
- }
- }
- }
-
// Insert PseudoReadVL after VLEFF/VLSEGFF and replace it with the vl output
// of VLEFF/VLSEGFF.
for (MachineBasicBlock &MBB : MF)
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 31119a403118fb4..30d559a4958c320 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -71,6 +71,13 @@ static cl::opt<bool> EnableRISCVCopyPropagation(
cl::desc("Enable the copy propagation with RISC-V copy instr"),
cl::init(true), cl::Hidden);
+static cl::opt<bool> EnableRISCVDeadRegisterElimination(
+ "riscv-enable-dead-defs", cl::Hidden,
+ cl::desc("Enable the pass that removes dead"
+ " definitons and replaces stores to"
+ " them with stores to x0"),
+ cl::init(true));
+
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
@@ -79,6 +86,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVO0PreLegalizerCombinerPass(*PR);
initializeRISCVPreLegalizerCombinerPass(*PR);
initializeKCFIPass(*PR);
+ initializeRISCVDeadRegisterDefinitionsPass(*PR);
initializeRISCVMakeCompressibleOptPass(*PR);
initializeRISCVGatherScatterLoweringPass(*PR);
initializeRISCVCodeGenPreparePass(*PR);
@@ -401,6 +409,9 @@ void RISCVPassConfig::addPreRegAlloc() {
if (TM->getOptLevel() != CodeGenOptLevel::None)
addPass(createRISCVMergeBaseOffsetOptPass());
addPass(createRISCVInsertVSETVLIPass());
+ if (TM->getOptLevel() != CodeGenOptLevel::None &&
+ EnableRISCVDeadRegisterElimination)
+ addPass(createRISCVDeadRegisterDefinitionsPass());
addPass(createRISCVInsertReadWriteCSRPass());
}
diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
index a9636cdf8bb17f3..277951782ce5ccb 100644
--- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -108,6 +108,7 @@
; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
; CHECK-NEXT: RISC-V Merge Base Offset
; CHECK-NEXT: RISC-V Insert VSETVLI pass
+; CHECK-NEXT: RISC-V Dead register definitions
; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
; CHECK-NEXT: Detect Dead Lanes
; CHECK-NEXT: RISC-V init undef pass
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll b/llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
index e952e71a5d736d2..895852b84e00417 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
@@ -7,12 +7,12 @@
define void @amoswap_w_discard(ptr %a, i32 %b) nounwind {
; RV32-LABEL: amoswap_w_discard:
; RV32: # %bb.0:
-; RV32-NEXT: amoswap.w.aqrl a0, a1, (a0)
+; RV32-NEXT: amoswap.w.aqrl zero, a1, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: amoswap_w_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amoswap.w.aqrl a0, a1, (a0)
+; RV64-NEXT: amoswap.w.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw xchg ptr %a, i32 %b seq_cst
ret void
@@ -31,7 +31,7 @@ define void @amoswap_d_discard(ptr %a, i64 %b) nounwind {
;
; RV64-LABEL: amoswap_d_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amoswap.d.aqrl a0, a1, (a0)
+; RV64-NEXT: amoswap.d.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw xchg ptr %a, i64 %b seq_cst
ret void
@@ -40,12 +40,12 @@ define void @amoswap_d_discard(ptr %a, i64 %b) nounwind {
define void @amoadd_w_discard(ptr %a, i32 %b) nounwind {
; RV32-LABEL: amoadd_w_discard:
; RV32: # %bb.0:
-; RV32-NEXT: amoadd.w.aqrl a0, a1, (a0)
+; RV32-NEXT: amoadd.w.aqrl zero, a1, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: amoadd_w_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amoadd.w.aqrl a0, a1, (a0)
+; RV64-NEXT: amoadd.w.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw add ptr %a, i32 %b seq_cst
ret void
@@ -64,7 +64,7 @@ define void @amoadd_d_discard(ptr %a, i64 %b) nounwind {
;
; RV64-LABEL: amoadd_d_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amoadd.d.aqrl a0, a1, (a0)
+; RV64-NEXT: amoadd.d.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw add ptr %a, i64 %b seq_cst
ret void
@@ -73,12 +73,12 @@ define void @amoadd_d_discard(ptr %a, i64 %b) nounwind {
define void @amoand_w_discard(ptr %a, i32 %b) nounwind {
; RV32-LABEL: amoand_w_discard:
; RV32: # %bb.0:
-; RV32-NEXT: amoand.w.aqrl a0, a1, (a0)
+; RV32-NEXT: amoand.w.aqrl zero, a1, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: amoand_w_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amoand.w.aqrl a0, a1, (a0)
+; RV64-NEXT: amoand.w.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw and ptr %a, i32 %b seq_cst
ret void
@@ -97,7 +97,7 @@ define void @amoand_d_discard(ptr %a, i64 %b) nounwind {
;
; RV64-LABEL: amoand_d_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amoand.d.aqrl a0, a1, (a0)
+; RV64-NEXT: amoand.d.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw and ptr %a, i64 %b seq_cst
ret void
@@ -106,12 +106,12 @@ define void @amoand_d_discard(ptr %a, i64 %b) nounwind {
define void @amoor_w_discard(ptr %a, i32 %b) nounwind {
; RV32-LABEL: amoor_w_discard:
; RV32: # %bb.0:
-; RV32-NEXT: amoor.w.aqrl a0, a1, (a0)
+; RV32-NEXT: amoor.w.aqrl zero, a1, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: amoor_w_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amoor.w.aqrl a0, a1, (a0)
+; RV64-NEXT: amoor.w.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw or ptr %a, i32 %b seq_cst
ret void
@@ -130,7 +130,7 @@ define void @amoor_d_discard(ptr %a, i64 %b) nounwind {
;
; RV64-LABEL: amoor_d_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amoor.d.aqrl a0, a1, (a0)
+; RV64-NEXT: amoor.d.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw or ptr %a, i64 %b seq_cst
ret void
@@ -139,12 +139,12 @@ define void @amoor_d_discard(ptr %a, i64 %b) nounwind {
define void @amoxor_w_discard(ptr %a, i32 %b) nounwind {
; RV32-LABEL: amoxor_w_discard:
; RV32: # %bb.0:
-; RV32-NEXT: amoor.w.aqrl a0, a1, (a0)
+; RV32-NEXT: amoor.w.aqrl zero, a1, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: amoxor_w_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amoor.w.aqrl a0, a1, (a0)
+; RV64-NEXT: amoor.w.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw or ptr %a, i32 %b seq_cst
ret void
@@ -163,7 +163,7 @@ define void @amoxor_d_discard(ptr %a, i64 %b) nounwind {
;
; RV64-LABEL: amoxor_d_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amoor.d.aqrl a0, a1, (a0)
+; RV64-NEXT: amoor.d.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw or ptr %a, i64 %b seq_cst
ret void
@@ -172,12 +172,12 @@ define void @amoxor_d_discard(ptr %a, i64 %b) nounwind {
define void @amomax_w_discard(ptr %a, i32 %b) nounwind {
; RV32-LABEL: amomax_w_discard:
; RV32: # %bb.0:
-; RV32-NEXT: amomax.w.aqrl a0, a1, (a0)
+; RV32-NEXT: amomax.w.aqrl zero, a1, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: amomax_w_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amomax.w.aqrl a0, a1, (a0)
+; RV64-NEXT: amomax.w.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw max ptr %a, i32 %b seq_cst
ret void
@@ -239,7 +239,7 @@ define void @amomax_d_discard(ptr %a, i64 %b) nounwind {
;
; RV64-LABEL: amomax_d_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amomax.d.aqrl a0, a1, (a0)
+; RV64-NEXT: amomax.d.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw max ptr %a, i64 %b seq_cst
ret void
@@ -248,12 +248,12 @@ define void @amomax_d_discard(ptr %a, i64 %b) nounwind {
define void @amomaxu_w_discard(ptr %a, i32 %b) nounwind {
; RV32-LABEL: amomaxu_w_discard:
; RV32: # %bb.0:
-; RV32-NEXT: amomaxu.w.aqrl a0, a1, (a0)
+; RV32-NEXT: amomaxu.w.aqrl zero, a1, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: amomaxu_w_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amomaxu.w.aqrl a0, a1, (a0)
+; RV64-NEXT: amomaxu.w.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw umax ptr %a, i32 %b seq_cst
ret void
@@ -315,7 +315,7 @@ define void @amomaxu_d_discard(ptr %a, i64 %b) nounwind {
;
; RV64-LABEL: amomaxu_d_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amomaxu.d.aqrl a0, a1, (a0)
+; RV64-NEXT: amomaxu.d.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw umax ptr %a, i64 %b seq_cst
ret void
@@ -324,12 +324,12 @@ define void @amomaxu_d_discard(ptr %a, i64 %b) nounwind {
define void @amomin_w_discard(ptr %a, i32 %b) nounwind {
; RV32-LABEL: amomin_w_discard:
; RV32: # %bb.0:
-; RV32-NEXT: amomin.w.aqrl a0, a1, (a0)
+; RV32-NEXT: amomin.w.aqrl zero, a1, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: amomin_w_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amomin.w.aqrl a0, a1, (a0)
+; RV64-NEXT: amomin.w.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw min ptr %a, i32 %b seq_cst
ret void
@@ -391,7 +391,7 @@ define void @amomin_d_discard(ptr %a, i64 %b) nounwind {
;
; RV64-LABEL: amomin_d_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amomin.d.aqrl a0, a1, (a0)
+; RV64-NEXT: amomin.d.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw min ptr %a, i64 %b seq_cst
ret void
@@ -400,12 +400,12 @@ define void @amomin_d_discard(ptr %a, i64 %b) nounwind {
define void @amominu_w_discard(ptr %a, i32 %b) nounwind {
; RV32-LABEL: amominu_w_discard:
; RV32: # %bb.0:
-; RV32-NEXT: amominu.w.aqrl a0, a1, (a0)
+; RV32-NEXT: amominu.w.aqrl zero, a1, (a0)
; RV32-NEXT: ret
;
; RV64-LABEL: amominu_w_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amominu.w.aqrl a0, a1, (a0)
+; RV64-NEXT: amominu.w.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw umin ptr %a, i32 %b seq_cst
ret void
@@ -467,7 +467,7 @@ define void @amominu_d_discard(ptr %a, i64 %b) nounwind {
;
; RV64-LABEL: amominu_d_discard:
; RV64: # %bb.0:
-; RV64-NEXT: amominu.d.aqrl a0, a1, (a0)
+; RV64-NEXT: amominu.d.aqrl zero, a1, (a0)
; RV64-NEXT: ret
%1 = atomicrmw umin ptr %a, i64 %b seq_cst
ret void
diff --git a/llvm/test/CodeGen/RISCV/branch.ll b/llvm/test/CodeGen/RISCV/branch.ll
index 492e47812b80f47..578080cd3a24044 100644
--- a/llvm/test/CodeGen/RISCV/branch.ll
+++ b/llvm/test/CodeGen/RISCV/branch.ll
@@ -35,7 +35,7 @@ define void @foo(i32 %a, ptr %b, i1 %c) nounwind {
; RV32I-NEXT: lw a3, 0(a1)
; RV32I-NEXT: bgeu a0, a3, .LBB0_14
; RV32I-NEXT: # %bb.10: # %test11
-; RV32I-NEXT: lw a0, 0(a1)
+; RV32I-NEXT: lw zero, 0(a1)
; RV32I-NEXT: andi a2, a2, 1
; RV32I-NEXT: bnez a2, .LBB0_14
; RV32I-NEXT: # %bb.11: # %test12
@@ -45,7 +45,7 @@ define void @foo(i32 %a, ptr %b, i1 %c) nounwind {
; RV32I-NEXT: lw a0, 0(a1)
; RV32I-NEXT: blez a0, .LBB0_14
; RV32I-NEXT: # %bb.13: # %test14
-; RV32I-NEXT: lw a0, 0(a1)
+; RV32I-NEXT: lw zero, 0(a1)
; RV32I-NEXT: .LBB0_14: # %end
; RV32I-NEXT: ret
%val1 = load volatile i32, ptr %b
diff --git a/llvm/test/CodeGen/RISCV/double-mem.ll b/llvm/test/CodeGen/RISCV/double-mem.ll
index b3f31730e711911..fb043f44beb39aa 100644
--- a/llvm/test/CodeGen/RISCV/double-mem.ll
+++ b/llvm/test/CodeGen/RISCV/double-mem.ll
@@ -136,10 +136,10 @@ define dso_local double @fld_fsd_global(double %a, double %b) nounwind {
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, a1
; RV64IZFINXZDINX-NEXT: lui a1, %hi(G)
-; RV64IZFINXZDINX-NEXT: ld a2, %lo(G)(a1)
+; RV64IZFINXZDINX-NEXT: ld zero, %lo(G)(a1)
; RV64IZFINXZDINX-NEXT: addi a2, a1, %lo(G)
; RV64IZFINXZDINX-NEXT: sd a0, %lo(G)(a1)
-; RV64IZFINXZDINX-NEXT: ld a1, 72(a2)
+; RV64IZFINXZDINX-NEXT: ld zero, 72(a2)
; RV64IZFINXZDINX-NEXT: sd a0, 72(a2)
; RV64IZFINXZDINX-NEXT: ret
; Use %a and %b in an FP op to ensure floating point registers are used, even
diff --git a/llvm/test/CodeGen/RISCV/float-mem.ll b/llvm/test/CodeGen/RISCV/float-mem.ll
index 8ef4f9162c2fe17..b5d5f8e7c7e6931 100644
--- a/llvm/test/CodeGen/RISCV/float-mem.ll
+++ b/llvm/test/CodeGen/RISCV/float-mem.ll
@@ -75,10 +75,10 @@ define dso_local float @flw_fsw_global(float %a, float %b) nounwind {
; CHECKIZFINX: # %bb.0:
; CHECKIZFINX-NEXT: fadd.s a0, a0, a1
; CHECKIZFINX-NEXT: lui a1, %hi(G)
-; CHECKIZFINX-NEXT: lw a2, %lo(G)(a1)
+; CHECKIZFINX-NEXT: lw zero, %lo(G)(a1)
; CHECKIZFINX-NEXT: addi a2, a1, %lo(G)
; CHECKIZFINX-NEXT: sw a0, %lo(G)(a1)
-; CHECKIZFINX-NEXT: lw a1, 36(a2)
+; CHECKIZFINX-NEXT: lw zero, 36(a2)
; CHECKIZFINX-NEXT: sw a0, 36(a2)
; CHECKIZFINX-NEXT: ret
%1 = fadd float %a, %b
diff --git a/llvm/test/CodeGen/RISCV/half-mem.ll b/llvm/test/CodeGen/RISCV/half-mem.ll
index 6688250999a75f4..35b129dfcdb7858 100644
--- a/llvm/test/CodeGen/RISCV/half-mem.ll
+++ b/llvm/test/CodeGen/RISCV/half-mem.ll
@@ -128,10 +128,10 @@ define half @flh_fsh_global(half %a, half %b) nounwind {
; CHECKIZHINX-NEXT: fadd.h a0, a0, a1
; CHECKIZHINX-NEXT: lui a1, %hi(G)
; CHECKIZHINX-NEXT: addi a1, a1, %lo(G)
-; CHECKIZHINX-NEXT: lh a2, 0(a1)
+; CHECKIZHINX-NEXT: lh zero, 0(a1)
; CHECKIZHINX-NEXT: sh a0, 0(a1)
; CHECKIZHINX-NEXT: addi a1, a1, 18
-; CHECKIZHINX-NEXT: lh a2, 0(a1)
+; CHECKIZHINX-NEXT: lh zero, 0(a1)
; CHECKIZHINX-NEXT: sh a0, 0(a1)
; CHECKIZHINX-NEXT: ret
;
@@ -157,10 +157,10 @@ define half @flh_fsh_global(half %a, half %b) nounwind {
; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: lui a1, %hi(G)
; CHECKIZHINXMIN-NEXT: addi a1, a1, %lo(G)
-; CHECKIZHINXMIN-NEXT: lh a2, 0(a1)
+; CHECKIZHINXMIN-NEXT: lh zero, 0(a1)
; CHECKIZHINXMIN-NEXT: sh a0, 0(a1)
; CHECKIZHINXMIN-NEXT: addi a1, a1, 18
-; CHECKIZHINXMIN-NEXT: lh a2, 0(a1)
+; CHECKIZHINXMIN-NEXT: lh zero, 0(a1)
; CHECKIZHINXMIN-NEXT: sh a0, 0(a1)
; CHECKIZHINXMIN-NEXT: ret
%1 = fadd half %a, %b
diff --git a/llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll b/llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
index ef64eeb9b18691a..40d08513e3cf37b 100644
--- a/llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
+++ b/llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
@@ -15,8 +15,8 @@ define void @use_frame_base_reg() {
; RV32I-NEXT: lui a0, 24
; RV32I-NEXT: addi a0, a0, 1704
; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: lbu a1, 4(a0)
-; RV32I-NEXT: lbu a0, 0(a0)
+; RV32I-NEXT: lbu zero, 4(a0)
+; RV32I-NEXT: lbu zero, 0(a0)
; RV32I-NEXT: lui a0, 24
; RV32I-NEXT: addi a0, a0, 1712
; RV32I-NEXT: add sp, sp, a0
@@ -31,8 +31,8 @@ define void @use_frame_base_reg() {
; RV64I-NEXT: lui a0, 24
; RV64I-NEXT: addiw a0, a0, 1704
; RV64I-NEXT: add a0, sp, a0
-; RV64I-NEXT: lbu a1, 4(a0)
-; RV64I-NEXT: lbu a0, 0(a0)
+; RV64I-NEXT: lbu zero, 4(a0)
+; RV64I-NEXT: lbu zero, 0(a0)
; RV64I-NEXT: lui a0, 24
; RV64I-NEXT: addiw a0, a0, 1712
; RV64I-NEXT: add sp, sp, a0
@@ -57,10 +57,10 @@ define void @load_with_offset() {
; RV32I-NEXT: .cfi_def_cfa_offset 100608
; RV32I-NEXT: lui a0, 25
; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: lbu a0, -292(a0)
+; RV32I-NEXT: lbu zero, -292(a0)
; RV32I-NEXT: lui a0, 24
; RV32I-NEXT: add a0, sp, a0
-; RV32I-NEXT: lbu a0, 1704(a0)
+; RV32I-NEXT: lbu zero, 1704(a0)
; RV32I-NEXT: lui a0, 25
; RV32I-NEXT: addi a0, a0, -1792
; RV32I-NEXT: add sp, sp, a0
@@ -74,10 +74,10 @@ define void @load_with_offset() {
; RV64I-NEXT: .cfi_def_cfa_offset 100608
; RV64I-NEXT: lui a0, 25
; RV64I-NEXT: add a0, sp, a0
-; RV64I-NEXT: lbu a0, -292(a0)
+; RV64I-NEXT: lbu zero, -292(a0)
; RV64I-NEXT: lui a0, 24
; RV64I-NEXT: add a0, sp, a0
-; RV64I-NEXT: lbu a0, 1704(a0)
+; RV64I-NEXT: lbu zero, 1704(a0)
; RV64I-NEXT: lui a0, 25
; RV64I-NEXT: addiw a0, a0, -1792
; RV64I-NEXT: add sp, sp, a0
diff --git a/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll b/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
index f6d69791e5d7cee..17167e7f51b4c7b 100644
--- a/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
+++ b/llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
@@ -16,7 +16,7 @@ define void @test_lla(i32 signext %n) {
; RV32I-NEXT: auipc a2, %pcrel_hi(l)
; RV32I-NEXT: .LBB0_1: # %loop
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: lw a3, %pcrel_lo(.Lpcrel_hi0)(a2)
+; RV32I-NEXT: lw zero, %pcrel_lo(.Lpcrel_hi0)(a2)
; RV32I-NEXT: addi a1, a1, 1
; RV32I-NEXT: blt a1, a0, .LBB0_1
; RV32I-NEXT: # %bb.2: # %ret
@@ -29,7 +29,7 @@ define void @test_lla(i32 signext %n) {
; RV64I-NEXT: auipc a2, %pcrel_hi(l)
; RV64I-NEXT: .LBB0_1: # %loop
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: lw a3, %pcrel_lo(.Lpcrel_hi0)(a2)
+; RV64I-NEXT: lw zero, %pcrel_lo(.Lpcrel_hi0)(a2)
; RV64I-NEXT: addiw a1, a1, 1
; RV64I-NEXT: blt a1, a0, .LBB0_1
; RV64I-NEXT: # %bb.2: # %ret
@@ -59,7 +59,7 @@ define void @test_la(i32 signext %n) {
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: .LBB1_1: # %loop
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: lw a3, 0(a1)
+; RV32I-NEXT: lw zero, 0(a1)
; RV32I-NEXT: addi a2, a2, 1
; RV32I-NEXT: blt a2, a0, .LBB1_1
; RV32I-NEXT: # %bb.2: # %ret
@@ -73,7 +73,7 @@ define void @test_la(i32 signext %n) {
; RV64I-NEXT: li a2, 0
; RV64I-NEXT: .LBB1_1: # %loop
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: lw a3, 0(a1)
+; RV64I-NEXT: lw zero, 0(a1)
; RV64I-NEXT: addiw a2, a2, 1
; RV64I-NEXT: blt a2, a0, .LBB1_1
; RV64I-NEXT: # %bb.2: # %ret
@@ -104,7 +104,7 @@ define void @test_la_tls_ie(i32 signext %n) {
; RV32I-NEXT: add a2, a2, tp
; RV32I-NEXT: .LBB2_1: # %loop
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: lw a3, 0(a2)
+; RV32I-NEXT: lw zero, 0(a2)
; RV32I-NEXT: addi a1, a1, 1
; RV32I-NEXT: blt a1, a0, .LBB2_1
; RV32I-NEXT: # %bb.2: # %ret
@@ -119,7 +119,7 @@ define void @test_la_tls_ie(i32 signext %n) {
; RV64I-NEXT: add a2, a2, tp
; RV64I-NEXT: .LBB2_1: # %loop
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: lw a3, 0(a2)
+; RV64I-NEXT: lw zero, 0(a2)
; RV64I-NEXT: addiw a1, a1, 1
; RV64I-NEXT: blt a1, a0, .LBB2_1
; RV64I-NEXT: # %bb.2: # %ret
@@ -157,7 +157,7 @@ define void @test_la_tls_gd(i32 signext %n) nounwind {
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __tls_get_addr at plt
-; RV32I-NEXT: lw a0, 0(a0)
+; RV32I-NEXT: lw zero, 0(a0)
; RV32I-NEXT: addi s2, s2, 1
; RV32I-NEXT: blt s2, s0, .LBB3_1
; RV32I-NEXT: # %bb.2: # %ret
@@ -184,7 +184,7 @@ define void @test_la_tls_gd(i32 signext %n) nounwind {
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __tls_get_addr at plt
-; RV64I-NEXT: lw a0, 0(a0)
+; RV64I-NEXT: lw zero, 0(a0)
; RV64I-NEXT: addiw s2, s2, 1
; RV64I-NEXT: blt s2, s0, .LBB3_1
; RV64I-NEXT: # %bb.2: # %ret
diff --git a/llvm/test/CodeGen/RISCV/mem.ll b/llvm/test/CodeGen/RISCV/mem.ll
index 74874c1ca74b3a5..3718ce80142d49a 100644
--- a/llvm/test/CodeGen/RISCV/mem.ll
+++ b/llvm/test/CodeGen/RISCV/mem.ll
@@ -8,7 +8,7 @@ define dso_local i32 @lb(ptr %a) nounwind {
; RV32I-LABEL: lb:
; RV32I: # %bb.0:
; RV32I-NEXT: lb a1, 1(a0)
-; RV32I-NEXT: lbu a0, 0(a0)
+; RV32I-NEXT: lbu zero, 0(a0)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret
%1 = getelementptr i8, ptr %a, i32 1
@@ -23,7 +23,7 @@ define dso_local i32 @lh(ptr %a) nounwind {
; RV32I-LABEL: lh:
; RV32I: # %bb.0:
; RV32I-NEXT: lh a1, 4(a0)
-; RV32I-NEXT: lh a0, 0(a0)
+; RV32I-NEXT: lh zero, 0(a0)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret
%1 = getelementptr i16, ptr %a, i32 2
@@ -38,7 +38,7 @@ define dso_local i32 @lw(ptr %a) nounwind {
; RV32I-LABEL: lw:
; RV32I: # %bb.0:
; RV32I-NEXT: lw a1, 12(a0)
-; RV32I-NEXT: lw a0, 0(a0)
+; RV32I-NEXT: lw zero, 0(a0)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret
%1 = getelementptr i32, ptr %a, i32 3
@@ -123,7 +123,7 @@ define dso_local i32 @load_sext_zext_anyext_i1(ptr %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: lbu a1, 1(a0)
; RV32I-NEXT: lbu a2, 2(a0)
-; RV32I-NEXT: lbu a0, 0(a0)
+; RV32I-NEXT: lbu zero, 0(a0)
; RV32I-NEXT: sub a0, a2, a1
; RV32I-NEXT: ret
; sextload i1
@@ -145,7 +145,7 @@ define dso_local i16 @load_sext_zext_anyext_i1_i16(ptr %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: lbu a1, 1(a0)
; RV32I-NEXT: lbu a2, 2(a0)
-; RV32I-NEXT: lbu a0, 0(a0)
+; RV32I-NEXT: lbu zero, 0(a0)
; RV32I-NEXT: sub a0, a2, a1
; RV32I-NEXT: ret
; sextload i1
@@ -172,7 +172,7 @@ define dso_local i32 @lw_sw_global(i32 %a) nounwind {
; RV32I-NEXT: lw a1, %lo(G)(a2)
; RV32I-NEXT: addi a3, a2, %lo(G)
; RV32I-NEXT: sw a0, %lo(G)(a2)
-; RV32I-NEXT: lw a2, 36(a3)
+; RV32I-NEXT: lw zero, 36(a3)
; RV32I-NEXT: sw a0, 36(a3)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/mem64.ll b/llvm/test/CodeGen/RISCV/mem64.ll
index 903c5b223b69c9a..09b04535498c5e6 100644
--- a/llvm/test/CodeGen/RISCV/mem64.ll
+++ b/llvm/test/CodeGen/RISCV/mem64.ll
@@ -8,7 +8,7 @@ define dso_local i64 @lb(ptr %a) nounwind {
; RV64I-LABEL: lb:
; RV64I: # %bb.0:
; RV64I-NEXT: lb a1, 1(a0)
-; RV64I-NEXT: lbu a0, 0(a0)
+; RV64I-NEXT: lbu zero, 0(a0)
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
%1 = getelementptr i8, ptr %a, i32 1
@@ -23,7 +23,7 @@ define dso_local i64 @lh(ptr %a) nounwind {
; RV64I-LABEL: lh:
; RV64I: # %bb.0:
; RV64I-NEXT: lh a1, 4(a0)
-; RV64I-NEXT: lh a0, 0(a0)
+; RV64I-NEXT: lh zero, 0(a0)
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
%1 = getelementptr i16, ptr %a, i32 2
@@ -38,7 +38,7 @@ define dso_local i64 @lw(ptr %a) nounwind {
; RV64I-LABEL: lw:
; RV64I: # %bb.0:
; RV64I-NEXT: lw a1, 12(a0)
-; RV64I-NEXT: lw a0, 0(a0)
+; RV64I-NEXT: lw zero, 0(a0)
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
%1 = getelementptr i32, ptr %a, i32 3
@@ -141,7 +141,7 @@ define dso_local i64 @ld(ptr %a) nounwind {
; RV64I-LABEL: ld:
; RV64I: # %bb.0:
; RV64I-NEXT: ld a1, 80(a0)
-; RV64I-NEXT: ld a0, 0(a0)
+; RV64I-NEXT: ld zero, 0(a0)
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
%1 = getelementptr i64, ptr %a, i32 10
@@ -168,7 +168,7 @@ define dso_local i64 @load_sext_zext_anyext_i1(ptr %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: lbu a1, 1(a0)
; RV64I-NEXT: lbu a2, 2(a0)
-; RV64I-NEXT: lbu a0, 0(a0)
+; RV64I-NEXT: lbu zero, 0(a0)
; RV64I-NEXT: sub a0, a2, a1
; RV64I-NEXT: ret
; sextload i1
@@ -190,7 +190,7 @@ define dso_local i16 @load_sext_zext_anyext_i1_i16(ptr %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: lbu a1, 1(a0)
; RV64I-NEXT: lbu a2, 2(a0)
-; RV64I-NEXT: lbu a0, 0(a0)
+; RV64I-NEXT: lbu zero, 0(a0)
; RV64I-NEXT: sub a0, a2, a1
; RV64I-NEXT: ret
; sextload i1
@@ -217,7 +217,7 @@ define dso_local i64 @ld_sd_global(i64 %a) nounwind {
; RV64I-NEXT: ld a1, %lo(G)(a2)
; RV64I-NEXT: addi a3, a2, %lo(G)
; RV64I-NEXT: sd a0, %lo(G)(a2)
-; RV64I-NEXT: ld a2, 72(a3)
+; RV64I-NEXT: ld zero, 72(a3)
; RV64I-NEXT: sd a0, 72(a3)
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/localvar.ll b/llvm/test/CodeGen/RISCV/rvv/localvar.ll
index 94118bfbce7b452..8c9a749d5ea16f7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/localvar.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/localvar.ll
@@ -162,7 +162,7 @@ define void @local_var_m2_mix_local_scalar() {
; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 4 * vlenb
-; RV64IV-NEXT: lw a0, 12(sp)
+; RV64IV-NEXT: lw zero, 12(sp)
; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 1
; RV64IV-NEXT: add a0, sp, a0
@@ -170,7 +170,7 @@ define void @local_var_m2_mix_local_scalar() {
; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: addi a0, sp, 16
; RV64IV-NEXT: vl2r.v v8, (a0)
-; RV64IV-NEXT: lw a0, 8(sp)
+; RV64IV-NEXT: lw zero, 8(sp)
; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: slli a0, a0, 2
; RV64IV-NEXT: add sp, sp, a0
@@ -271,11 +271,11 @@ define void @local_var_m2_with_bp(i64 %n) {
; RV64IV-NEXT: add s2, s1, s2
; RV64IV-NEXT: addi s2, s2, 224
; RV64IV-NEXT: call notdead2 at plt
-; RV64IV-NEXT: lw a0, 124(s1)
+; RV64IV-NEXT: lw zero, 124(s1)
; RV64IV-NEXT: vl2r.v v8, (s2)
; RV64IV-NEXT: addi a0, s1, 224
; RV64IV-NEXT: vl2r.v v8, (a0)
-; RV64IV-NEXT: lw a0, 120(s1)
+; RV64IV-NEXT: lw zero, 120(s1)
; RV64IV-NEXT: addi sp, s0, -256
; RV64IV-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
index 87b4e60aaca2cf8..191d932923eb518 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
@@ -27,7 +27,7 @@ define void @rvv_vla(i64 %n, i64 %i) nounwind {
; CHECK-NEXT: vl2re64.v v8, (a2)
; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: lw a0, 0(a0)
+; CHECK-NEXT: lw zero, 0(a0)
; CHECK-NEXT: addi sp, s0, -32
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
@@ -65,7 +65,7 @@ define void @rvv_overaligned() nounwind {
; CHECK-NEXT: vl1re64.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 112
; CHECK-NEXT: vl2re64.v v8, (a0)
-; CHECK-NEXT: lw a0, 64(sp)
+; CHECK-NEXT: lw zero, 64(sp)
; CHECK-NEXT: addi sp, s0, -128
; CHECK-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
@@ -109,10 +109,10 @@ define void @rvv_vla_and_overaligned(i64 %n, i64 %i) nounwind {
; CHECK-NEXT: vl1re64.v v8, (a2)
; CHECK-NEXT: addi a2, s1, 112
; CHECK-NEXT: vl2re64.v v8, (a2)
-; CHECK-NEXT: lw a2, 64(s1)
+; CHECK-NEXT: lw zero, 64(s1)
; CHECK-NEXT: slli a1, a1, 2
; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: lw a0, 0(a0)
+; CHECK-NEXT: lw zero, 0(a0)
; CHECK-NEXT: addi sp, s0, -144
; CHECK-NEXT: ld ra, 136(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 128(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
index d7e5140501de160..3eb37605a96b34a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
@@ -3,7 +3,6 @@
# RUN: -run-pass=riscv-insert-vsetvli | FileCheck %s
--- |
- ; ModuleID = 'vsetvli-insert.ll'
source_filename = "vsetvli-insert.ll"
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
target triple = "riscv64"
@@ -47,7 +46,6 @@
ret void
}
- ; Function Attrs: nounwind readnone
declare i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64>) #1
define i64 @vmv_x_s(i8 zeroext %cond, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) #0 {
@@ -69,7 +67,6 @@
ret i64 %d
}
- ; Function Attrs: nounwind
declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #2
define <vscale x 1 x i64> @vsetvli_add_or_sub(i8 zeroext %cond, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %avl) #0 {
@@ -133,28 +130,20 @@
ret void
}
- ; Function Attrs: nofree nosync nounwind readnone willreturn
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
- ; Function Attrs: nounwind readnone
declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
- ; Function Attrs: nounwind readnone
declare <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i64>, i64) #1
- ; Function Attrs: nounwind readonly
declare <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>* nocapture, i64) #3
- ; Function Attrs: nounwind readonly
declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32>, <vscale x 1 x i32>* nocapture, i64) #3
- ; Function Attrs: nounwind writeonly
declare void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64>, <vscale x 1 x i64>* nocapture, i64) #4
- ; Function Attrs: nounwind readnone
declare <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
- ; Function Attrs: nounwind readnone
declare <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64>, <vscale x 1 x i32>, i64) #1
attributes #0 = { "target-features"="+v" }
@@ -452,7 +441,7 @@ body: |
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: $x0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: [[PseudoVSETVLI:%[0-9]+]]:gprnox0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: BEQ [[COPY3]], [[COPY4]], %bb.2
; CHECK-NEXT: PseudoBR %bb.1
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
index 05453ed0385472f..7bda7a387c68f96 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
@@ -362,7 +362,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8
- ; CHECK-NEXT: $x0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: [[PseudoVSETVLI:%[0-9]+]]:gprnox0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]]
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