[llvm] [RISCV] Use LMUL=1 for vmv_s_x_vl with non-undef passthru (PR #66659)

[Philip Reames via llvm-commits]

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@@ -550,9 +550,9 @@ define void @insertelt_c6_v8i64_0_add(ptr %x, ptr %y) {
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    li a2, 6
-; CHECK-NEXT:    vsetvli zero, zero, e64, m4, tu, ma
+; CHECK-NEXT:    vsetivli zero, 8, e64, m1, tu, ma
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preames wrote:

> I see what you mean about the legality though: Does the register allocator here know not to allocate v1/v2/v3 etc for %6, given its vtype will be M4?

I think I'm wrong here and I sent you on a wild goose chase.  The specification says for vmv.s.x that "The instructions ignore LMUL and vector register groups.".  I think that means these are unconditionally m1 (from an encoding legality perspective) even if LMUL is set to m4.  

https://github.com/llvm/llvm-project/pull/66659