[PATCH] D159533: [DAG] getNode() - fold (zext (trunc x)) -> x iff the upper bits are known zero - add SRL support

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In D159533#4649980 <https://reviews.llvm.org/D159533#4649980>, @foad wrote:

> @jrbyrnes shouldn't we land the AMDGPU changes separately first? Or would it all be dead code without the rest of this patch?

I can pre-commit the matchPERM helper as a NFC-ish to reduce the diff if that helps?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159533/new/

https://reviews.llvm.org/D159533