[llvm] [RISCV] Combine vmv.s.x to vmv.v.i if VL is known > 0 (PR #67155)
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Fri Sep 22 08:34:55 PDT 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
<details>
<summary>Changes</summary>
We currently combine vmv.s.x with an undef passthru to vmv.v.i. Assuming a VL
toggle is cheaper than a li, we can also do this if the passthru isn't undef by
setting VL=1, provided that we know VL > 0 to begin with. (vmv.s.x has only two
behaviours with respect to VL: VL = 0, and VL > 0)
---
Full diff: https://github.com/llvm/llvm-project/pull/67155.diff
2 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+10-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll (+6-8)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 8b745b2afaf956b..d14ca45821888bb 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14480,8 +14480,16 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
// no purpose.
if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Scalar);
Const && !Const->isZero() && isInt<5>(Const->getSExtValue()) &&
- VT.bitsLE(getLMUL1VT(VT)) && Passthru.isUndef())
- return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Passthru, Scalar, VL);
+ VT.bitsLE(getLMUL1VT(VT))) {
+ if (Passthru.isUndef())
+ return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Passthru, Scalar, VL);
+
+ // If we know VL isn't zero, then we can use VL=1.
+ if (isa<ConstantSDNode>(VL) &&
+ cast<ConstantSDNode>(VL)->getZExtValue() > 0)
+ return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Passthru, Scalar,
+ DAG.getVectorIdxConstant(1, DL));
+ }
break;
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
index 78cafbb84bb926e..c16df830073f110 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
@@ -361,10 +361,9 @@ define <8 x i8> @splat_ve4_ins_i0ve2(<8 x i8> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 4
-; CHECK-NEXT: li a0, 2
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, tu, ma
-; CHECK-NEXT: vmv.s.x v10, a0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
+; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, ma
+; CHECK-NEXT: vmv.v.i v10, 2
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
@@ -407,10 +406,9 @@ define <8 x i8> @splat_ve2_we0_ins_i0ve4(<8 x i8> %v, <8 x i8> %w) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v11, 2
-; CHECK-NEXT: li a0, 4
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, tu, ma
-; CHECK-NEXT: vmv.s.x v11, a0
-; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu
+; CHECK-NEXT: vsetivli zero, 1, e8, mf2, tu, ma
+; CHECK-NEXT: vmv.v.i v11, 4
+; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: li a0, 66
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vrgather.vv v10, v8, v11
``````````
</details>
https://github.com/llvm/llvm-project/pull/67155
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