[llvm] [RISCV][GISel] Remove source constraint from selectCopy and use it fo… (PR #67207)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 22 16:29:53 PDT 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
<details>
<summary>Changes</summary>
…r G_ANYEXT/G_TRUNC.
AArch64, Mips, and ARM do not have source constraints in their version of selectCopy. I'm assuming we don't need it either.
We weren't constraining the destination register of G_ANYEXT/G_TRUNC previously, but we got away with it in our tests because all their users constrained them as a use. When I removed the source constraint from selectCopy this stopped working.
---
Full diff: https://github.com/llvm/llvm-project/pull/67207.diff
1 Files Affected:
- (modified) llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp (+15-28)
``````````diff
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index a6163396b72d72f..8e78bd3389cbaf3 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -225,8 +225,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
switch (Opc) {
case TargetOpcode::G_ANYEXT:
case TargetOpcode::G_TRUNC:
- MI.setDesc(TII.get(TargetOpcode::COPY));
- return true;
+ return selectCopy(MI, MRI);
case TargetOpcode::G_CONSTANT:
if (!selectConstant(MI, MIB, MRI))
return false;
@@ -271,37 +270,25 @@ const TargetRegisterClass *RISCVInstructionSelector::getRegClassForTypeOnBank(
bool RISCVInstructionSelector::selectCopy(MachineInstr &MI,
MachineRegisterInfo &MRI) const {
Register DstReg = MI.getOperand(0).getReg();
- Register SrcReg = MI.getOperand(1).getReg();
- if (Register::isPhysicalRegister(SrcReg) &&
- Register::isPhysicalRegister(DstReg))
+ if (DstReg.isPhysical())
return true;
- if (!Register::isPhysicalRegister(SrcReg)) {
- const TargetRegisterClass *SrcRC = getRegClassForTypeOnBank(
- MRI.getType(SrcReg), *RBI.getRegBank(SrcReg, MRI, TRI));
- assert(SrcRC &&
- "Register class not available for LLT, register bank combination");
-
- if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, MRI)) {
- LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(MI.getOpcode())
- << " operand\n");
- return false;
- }
- }
- if (!Register::isPhysicalRegister(DstReg)) {
- const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(
- MRI.getType(DstReg), *RBI.getRegBank(DstReg, MRI, TRI));
- assert(DstRC &&
- "Register class not available for LLT, register bank combination");
-
- if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
- LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(MI.getOpcode())
- << " operand\n");
- return false;
- }
+ const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(
+ MRI.getType(DstReg), *RBI.getRegBank(DstReg, MRI, TRI));
+ assert(DstRC &&
+ "Register class not available for LLT, register bank combination");
+
+ // No need to constrain SrcReg. It will get constrained when
+ // we hit another of its uses or its defs.
+ // Copies do not have constraints.
+ if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) {
+ LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(MI.getOpcode())
+ << " operand\n");
+ return false;
}
+ MI.setDesc(TII.get(RISCV::COPY));
return true;
}
``````````
</details>
https://github.com/llvm/llvm-project/pull/67207
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