[llvm] 9a04bc4 - [AArch64] Move LDR_PXI from isStoreToStackSlot to isLoadFromStackSlot (#65658)

[via llvm-commits]

Author: weiguozhi
Date: 2023-09-18T15:52:41-07:00
New Revision: 9a04bc4c43f7a0a556765869c49d9a10473b40f2

URL: https://github.com/llvm/llvm-project/commit/9a04bc4c43f7a0a556765869c49d9a10473b40f2
DIFF: https://github.com/llvm/llvm-project/commit/9a04bc4c43f7a0a556765869c49d9a10473b40f2.diff

LOG: [AArch64] Move LDR_PXI from isStoreToStackSlot to isLoadFromStackSlot (#65658)

LDR_PXI is a load instruction, so it should be in isLoadFromStackSlot.

Added: 
    llvm/test/CodeGen/AArch64/spill-reload-remarks.ll

Modified: 
    llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index 5ad2e4837e3db4e..bceea75f278221a 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -2234,6 +2234,7 @@ unsigned AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
   case AArch64::LDRSui:
   case AArch64::LDRDui:
   case AArch64::LDRQui:
+  case AArch64::LDR_PXI:
     if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
         MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {
       FrameIndex = MI.getOperand(1).getIndex();
@@ -2257,7 +2258,6 @@ unsigned AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
   case AArch64::STRSui:
   case AArch64::STRDui:
   case AArch64::STRQui:
-  case AArch64::LDR_PXI:
   case AArch64::STR_PXI:
     if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
         MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0) {

diff  --git a/llvm/test/CodeGen/AArch64/spill-reload-remarks.ll b/llvm/test/CodeGen/AArch64/spill-reload-remarks.ll
new file mode 100644
index 000000000000000..47906252382f4c4
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/spill-reload-remarks.ll
@@ -0,0 +1,15 @@
+; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -mattr=+sme -pass-remarks-missed='regalloc' %s -o - 2>&1 | FileCheck %s
+
+; We should have both spill and reload for %arg.
+
+; CHECK: remark: <unknown>:0:0: 2 spills 2.000000e+00 total spills cost 3 reloads 3.000000e+00 total reloads cost generated in function
+
+define <vscale x 2 x i1> @streaming_compatible_with_predicate_vectors(<vscale x 2 x i1> %arg) "aarch64_pstate_sm_compatible" nounwind #0 {
+  %res = call <vscale x 2 x i1> @normal_callee_predicate_vec_arg(<vscale x 2 x i1> %arg)
+  %and = and <vscale x 2 x i1> %res, %arg
+  ret <vscale x 2 x i1> %and
+}
+
+declare <vscale x 2 x i1> @normal_callee_predicate_vec_arg(<vscale x 2 x i1>)
+
+attributes #0 = { nounwind "target-features"="+sve" }