[llvm] [RISCV] Add more instructions for the short forward branch optimization. (PR #66789)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 19 09:35:53 PDT 2023
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
<details>
<summary>Changes</summary>
This adds the shifts and the immediate forms of the instructions that were already supported.
There are still more instructions that can be predicated, but this is the rest of what we had in our downstream.
---
Patch is 23.08 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/66789.diff
4 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp (+34)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+23)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+87)
- (modified) llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll (+410-4)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index 58896ee1b388f5d..ff35a8fc9c5a1e0 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -119,6 +119,23 @@ bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
case RISCV::PseudoCCXOR:
case RISCV::PseudoCCADDW:
case RISCV::PseudoCCSUBW:
+ case RISCV::PseudoCCSLL:
+ case RISCV::PseudoCCSRL:
+ case RISCV::PseudoCCSRA:
+ case RISCV::PseudoCCADDI:
+ case RISCV::PseudoCCSLLI:
+ case RISCV::PseudoCCSRLI:
+ case RISCV::PseudoCCSRAI:
+ case RISCV::PseudoCCANDI:
+ case RISCV::PseudoCCORI:
+ case RISCV::PseudoCCXORI:
+ case RISCV::PseudoCCSLLW:
+ case RISCV::PseudoCCSRLW:
+ case RISCV::PseudoCCSRAW:
+ case RISCV::PseudoCCADDIW:
+ case RISCV::PseudoCCSLLIW:
+ case RISCV::PseudoCCSRLIW:
+ case RISCV::PseudoCCSRAIW:
return expandCCOp(MBB, MBBI, NextMBBI);
case RISCV::PseudoVSETVLI:
case RISCV::PseudoVSETVLIX0:
@@ -188,11 +205,28 @@ bool RISCVExpandPseudo::expandCCOp(MachineBasicBlock &MBB,
llvm_unreachable("Unexpected opcode!");
case RISCV::PseudoCCADD: NewOpc = RISCV::ADD; break;
case RISCV::PseudoCCSUB: NewOpc = RISCV::SUB; break;
+ case RISCV::PseudoCCSLL: NewOpc = RISCV::SLL; break;
+ case RISCV::PseudoCCSRL: NewOpc = RISCV::SRL; break;
+ case RISCV::PseudoCCSRA: NewOpc = RISCV::SRA; break;
case RISCV::PseudoCCAND: NewOpc = RISCV::AND; break;
case RISCV::PseudoCCOR: NewOpc = RISCV::OR; break;
case RISCV::PseudoCCXOR: NewOpc = RISCV::XOR; break;
+ case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break;
+ case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break;
+ case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break;
+ case RISCV::PseudoCCSRAI: NewOpc = RISCV::SRAI; break;
+ case RISCV::PseudoCCANDI: NewOpc = RISCV::ANDI; break;
+ case RISCV::PseudoCCORI: NewOpc = RISCV::ORI; break;
+ case RISCV::PseudoCCXORI: NewOpc = RISCV::XORI; break;
case RISCV::PseudoCCADDW: NewOpc = RISCV::ADDW; break;
case RISCV::PseudoCCSUBW: NewOpc = RISCV::SUBW; break;
+ case RISCV::PseudoCCSLLW: NewOpc = RISCV::SLLW; break;
+ case RISCV::PseudoCCSRLW: NewOpc = RISCV::SRLW; break;
+ case RISCV::PseudoCCSRAW: NewOpc = RISCV::SRAW; break;
+ case RISCV::PseudoCCADDIW: NewOpc = RISCV::ADDIW; break;
+ case RISCV::PseudoCCSLLIW: NewOpc = RISCV::SLLIW; break;
+ case RISCV::PseudoCCSRLIW: NewOpc = RISCV::SRLIW; break;
+ case RISCV::PseudoCCSRAIW: NewOpc = RISCV::SRAIW; break;
}
BuildMI(TrueBB, DL, TII->get(NewOpc), DestReg)
.add(MI.getOperand(5))
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 14f1bff4aee4ca8..816ceaf95607e71 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1106,12 +1106,31 @@ unsigned getPredicatedOpcode(unsigned Opcode) {
switch (Opcode) {
case RISCV::ADD: return RISCV::PseudoCCADD; break;
case RISCV::SUB: return RISCV::PseudoCCSUB; break;
+ case RISCV::SLL: return RISCV::PseudoCCSLL; break;
+ case RISCV::SRL: return RISCV::PseudoCCSRL; break;
+ case RISCV::SRA: return RISCV::PseudoCCSRA; break;
case RISCV::AND: return RISCV::PseudoCCAND; break;
case RISCV::OR: return RISCV::PseudoCCOR; break;
case RISCV::XOR: return RISCV::PseudoCCXOR; break;
+ case RISCV::ADDI: return RISCV::PseudoCCADDI; break;
+ case RISCV::SLLI: return RISCV::PseudoCCSLLI; break;
+ case RISCV::SRLI: return RISCV::PseudoCCSRLI; break;
+ case RISCV::SRAI: return RISCV::PseudoCCSRAI; break;
+ case RISCV::ANDI: return RISCV::PseudoCCANDI; break;
+ case RISCV::ORI: return RISCV::PseudoCCORI; break;
+ case RISCV::XORI: return RISCV::PseudoCCXORI; break;
+
case RISCV::ADDW: return RISCV::PseudoCCADDW; break;
case RISCV::SUBW: return RISCV::PseudoCCSUBW; break;
+ case RISCV::SLLW: return RISCV::PseudoCCSLLW; break;
+ case RISCV::SRLW: return RISCV::PseudoCCSRLW; break;
+ case RISCV::SRAW: return RISCV::PseudoCCSRAW; break;
+
+ case RISCV::ADDIW: return RISCV::PseudoCCADDIW; break;
+ case RISCV::SLLIW: return RISCV::PseudoCCSLLIW; break;
+ case RISCV::SRLIW: return RISCV::PseudoCCSRLIW; break;
+ case RISCV::SRAIW: return RISCV::PseudoCCSRAIW; break;
}
return RISCV::INSTRUCTION_LIST_END;
@@ -1132,6 +1151,10 @@ static MachineInstr *canFoldAsPredicatedOp(Register Reg,
// Check if MI can be predicated and folded into the CCMOV.
if (getPredicatedOpcode(MI->getOpcode()) == RISCV::INSTRUCTION_LIST_END)
return nullptr;
+ // Don't predicate li idiom.
+ if (MI->getOpcode() == RISCV::ADDI && MI->getOperand(1).isReg() &&
+ MI->getOperand(1).getReg() == RISCV::X0)
+ return nullptr;
// Check if MI has any other defs or physreg uses.
for (const MachineOperand &MO : llvm::drop_begin(MI->operands())) {
// Reject frame index operands, PEI can't handle the predicated pseudos.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 582fe60fd0368e9..abbeff78b6e2864 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1438,6 +1438,21 @@ def PseudoCCSUB : Pseudo<(outs GPR:$dst),
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
+def PseudoCCSLL : Pseudo<(outs GPR:$dst),
+ (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
+ GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
+ Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
+ ReadSFBALU, ReadSFBALU]>;
+def PseudoCCSRL : Pseudo<(outs GPR:$dst),
+ (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
+ GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
+ Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
+ ReadSFBALU, ReadSFBALU]>;
+def PseudoCCSRA : Pseudo<(outs GPR:$dst),
+ (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
+ GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
+ Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
+ ReadSFBALU, ReadSFBALU]>;
def PseudoCCAND : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
@@ -1454,6 +1469,42 @@ def PseudoCCXOR : Pseudo<(outs GPR:$dst),
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
+def PseudoCCADDI : Pseudo<(outs GPR:$dst),
+ (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
+ GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
+ Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
+ ReadSFBALU]>;
+def PseudoCCSLLI : Pseudo<(outs GPR:$dst),
+ (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
+ GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
+ Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
+ ReadSFBALU]>;
+def PseudoCCSRLI : Pseudo<(outs GPR:$dst),
+ (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
+ GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
+ Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
+ ReadSFBALU]>;
+def PseudoCCSRAI : Pseudo<(outs GPR:$dst),
+ (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
+ GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
+ Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
+ ReadSFBALU]>;
+def PseudoCCANDI : Pseudo<(outs GPR:$dst),
+ (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
+ GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
+ Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
+ ReadSFBALU]>;
+def PseudoCCORI : Pseudo<(outs GPR:$dst),
+ (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
+ GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
+ Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
+ ReadSFBALU]>;
+def PseudoCCXORI : Pseudo<(outs GPR:$dst),
+ (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
+ GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
+ Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
+ ReadSFBALU]>;
+
// RV64I instructions
def PseudoCCADDW : Pseudo<(outs GPR:$dst),
(ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
@@ -1465,6 +1516,42 @@ def PseudoCCSUBW : Pseudo<(outs GPR:$dst),
GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp,
ReadSFBALU, ReadSFBALU, ReadSFBALU]>;
+def PseudoCCSLLW : Pseudo<(outs GPR:$dst),
+ (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
+ GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
+ Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
+ ReadSFBALU, ReadSFBALU]>;
+def PseudoCCSRLW : Pseudo<(outs GPR:$dst),
+ (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
+ GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
+ Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
+ ReadSFBALU, ReadSFBALU]>;
+def PseudoCCSRAW : Pseudo<(outs GPR:$dst),
+ (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
+ GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
+ Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
+ ReadSFBALU, ReadSFBALU]>;
+
+def PseudoCCADDIW : Pseudo<(outs GPR:$dst),
+ (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
+ GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
+ Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
+ ReadSFBALU]>;
+def PseudoCCSLLIW : Pseudo<(outs GPR:$dst),
+ (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
+ GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
+ Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
+ ReadSFBALU]>;
+def PseudoCCSRLIW : Pseudo<(outs GPR:$dst),
+ (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
+ GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
+ Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
+ ReadSFBALU]>;
+def PseudoCCSRAIW : Pseudo<(outs GPR:$dst),
+ (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc,
+ GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
+ Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU,
+ ReadSFBALU]>;
}
multiclass SelectCC_GPR_rrirr<DAGOperand valty, ValueType vt> {
diff --git a/llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll b/llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll
index 862c366b553f872..a91f726eb06df2e 100644
--- a/llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll
+++ b/llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll
@@ -192,10 +192,9 @@ define i16 @select_xor_1(i16 %A, i8 %cond) {
; SFB-LABEL: select_xor_1:
; SFB: # %bb.0: # %entry
; SFB-NEXT: andi a1, a1, 1
-; SFB-NEXT: xori a2, a0, 43
; SFB-NEXT: beqz a1, .LBB7_2
; SFB-NEXT: # %bb.1: # %entry
-; SFB-NEXT: mv a0, a2
+; SFB-NEXT: xori a0, a0, 43
; SFB-NEXT: .LBB7_2: # %entry
; SFB-NEXT: ret
entry:
@@ -220,10 +219,9 @@ define i16 @select_xor_1b(i16 %A, i8 %cond) {
; SFB-LABEL: select_xor_1b:
; SFB: # %bb.0: # %entry
; SFB-NEXT: andi a1, a1, 1
-; SFB-NEXT: xori a2, a0, 43
; SFB-NEXT: beqz a1, .LBB8_2
; SFB-NEXT: # %bb.1: # %entry
-; SFB-NEXT: mv a0, a2
+; SFB-NEXT: xori a0, a0, 43
; SFB-NEXT: .LBB8_2: # %entry
; SFB-NEXT: ret
entry:
@@ -522,3 +520,411 @@ bb2: ; preds = %bb2, %bb
bb7: ; preds = %bb2
ret void
}
+
+define i32 @select_sllw(i32 %A, i32 %B, i32 %C, i1 zeroext %cond) {
+; NOSFB-LABEL: select_sllw:
+; NOSFB: # %bb.0: # %entry
+; NOSFB-NEXT: bnez a3, .LBB17_2
+; NOSFB-NEXT: # %bb.1: # %entry
+; NOSFB-NEXT: sllw a2, a0, a1
+; NOSFB-NEXT: .LBB17_2: # %entry
+; NOSFB-NEXT: mv a0, a2
+; NOSFB-NEXT: ret
+;
+; SFB-LABEL: select_sllw:
+; SFB: # %bb.0: # %entry
+; SFB-NEXT: bnez a3, .LBB17_2
+; SFB-NEXT: # %bb.1: # %entry
+; SFB-NEXT: sllw a2, a0, a1
+; SFB-NEXT: .LBB17_2: # %entry
+; SFB-NEXT: mv a0, a2
+; SFB-NEXT: ret
+entry:
+ %0 = shl i32 %A, %B
+ %1 = select i1 %cond, i32 %C, i32 %0
+ ret i32 %1
+}
+
+define i32 @select_srlw(i32 %A, i32 %B, i32 %C, i1 zeroext %cond) {
+; NOSFB-LABEL: select_srlw:
+; NOSFB: # %bb.0: # %entry
+; NOSFB-NEXT: bnez a3, .LBB18_2
+; NOSFB-NEXT: # %bb.1: # %entry
+; NOSFB-NEXT: srlw a2, a0, a1
+; NOSFB-NEXT: .LBB18_2: # %entry
+; NOSFB-NEXT: mv a0, a2
+; NOSFB-NEXT: ret
+;
+; SFB-LABEL: select_srlw:
+; SFB: # %bb.0: # %entry
+; SFB-NEXT: bnez a3, .LBB18_2
+; SFB-NEXT: # %bb.1: # %entry
+; SFB-NEXT: srlw a2, a0, a1
+; SFB-NEXT: .LBB18_2: # %entry
+; SFB-NEXT: mv a0, a2
+; SFB-NEXT: ret
+entry:
+ %0 = lshr i32 %A, %B
+ %1 = select i1 %cond, i32 %C, i32 %0
+ ret i32 %1
+}
+
+define i32 @select_sraw(i32 %A, i32 %B, i32 %C, i1 zeroext %cond) {
+; NOSFB-LABEL: select_sraw:
+; NOSFB: # %bb.0: # %entry
+; NOSFB-NEXT: bnez a3, .LBB19_2
+; NOSFB-NEXT: # %bb.1: # %entry
+; NOSFB-NEXT: sraw a2, a0, a1
+; NOSFB-NEXT: .LBB19_2: # %entry
+; NOSFB-NEXT: mv a0, a2
+; NOSFB-NEXT: ret
+;
+; SFB-LABEL: select_sraw:
+; SFB: # %bb.0: # %entry
+; SFB-NEXT: bnez a3, .LBB19_2
+; SFB-NEXT: # %bb.1: # %entry
+; SFB-NEXT: sraw a2, a0, a1
+; SFB-NEXT: .LBB19_2: # %entry
+; SFB-NEXT: mv a0, a2
+; SFB-NEXT: ret
+entry:
+ %0 = ashr i32 %A, %B
+ %1 = select i1 %cond, i32 %C, i32 %0
+ ret i32 %1
+}
+
+define i64 @select_sll(i64 %A, i64 %B, i64 %C, i1 zeroext %cond) {
+; NOSFB-LABEL: select_sll:
+; NOSFB: # %bb.0: # %entry
+; NOSFB-NEXT: bnez a3, .LBB20_2
+; NOSFB-NEXT: # %bb.1: # %entry
+; NOSFB-NEXT: sll a2, a0, a1
+; NOSFB-NEXT: .LBB20_2: # %entry
+; NOSFB-NEXT: mv a0, a2
+; NOSFB-NEXT: ret
+;
+; SFB-LABEL: select_sll:
+; SFB: # %bb.0: # %entry
+; SFB-NEXT: bnez a3, .LBB20_2
+; SFB-NEXT: # %bb.1: # %entry
+; SFB-NEXT: sll a2, a0, a1
+; SFB-NEXT: .LBB20_2: # %entry
+; SFB-NEXT: mv a0, a2
+; SFB-NEXT: ret
+entry:
+ %0 = shl i64 %A, %B
+ %1 = select i1 %cond, i64 %C, i64 %0
+ ret i64 %1
+}
+
+define i64 @select_srl(i64 %A, i64 %B, i64 %C, i1 zeroext %cond) {
+; NOSFB-LABEL: select_srl:
+; NOSFB: # %bb.0: # %entry
+; NOSFB-NEXT: bnez a3, .LBB21_2
+; NOSFB-NEXT: # %bb.1: # %entry
+; NOSFB-NEXT: srl a2, a0, a1
+; NOSFB-NEXT: .LBB21_2: # %entry
+; NOSFB-NEXT: mv a0, a2
+; NOSFB-NEXT: ret
+;
+; SFB-LABEL: select_srl:
+; SFB: # %bb.0: # %entry
+; SFB-NEXT: bnez a3, .LBB21_2
+; SFB-NEXT: # %bb.1: # %entry
+; SFB-NEXT: srl a2, a0, a1
+; SFB-NEXT: .LBB21_2: # %entry
+; SFB-NEXT: mv a0, a2
+; SFB-NEXT: ret
+entry:
+ %0 = lshr i64 %A, %B
+ %1 = select i1 %cond, i64 %C, i64 %0
+ ret i64 %1
+}
+
+define i64 @select_sra(i64 %A, i64 %B, i64 %C, i1 zeroext %cond) {
+; NOSFB-LABEL: select_sra:
+; NOSFB: # %bb.0: # %entry
+; NOSFB-NEXT: bnez a3, .LBB22_2
+; NOSFB-NEXT: # %bb.1: # %entry
+; NOSFB-NEXT: sra a2, a0, a1
+; NOSFB-NEXT: .LBB22_2: # %entry
+; NOSFB-NEXT: mv a0, a2
+; NOSFB-NEXT: ret
+;
+; SFB-LABEL: select_sra:
+; SFB: # %bb.0: # %entry
+; SFB-NEXT: bnez a3, .LBB22_2
+; SFB-NEXT: # %bb.1: # %entry
+; SFB-NEXT: sra a2, a0, a1
+; SFB-NEXT: .LBB22_2: # %entry
+; SFB-NEXT: mv a0, a2
+; SFB-NEXT: ret
+entry:
+ %0 = ashr i64 %A, %B
+ %1 = select i1 %cond, i64 %C, i64 %0
+ ret i64 %1
+}
+
+define i32 @select_addiw(i32 %A, i32 %C, i1 zeroext %cond) {
+; NOSFB-LABEL: select_addiw:
+; NOSFB: # %bb.0: # %entry
+; NOSFB-NEXT: bnez a2, .LBB23_2
+; NOSFB-NEXT: # %bb.1: # %entry
+; NOSFB-NEXT: addiw a1, a0, 1234
+; NOSFB-NEXT: .LBB23_2: # %entry
+; NOSFB-NEXT: mv a0, a1
+; NOSFB-NEXT: ret
+;
+; SFB-LABEL: select_addiw:
+; SFB: # %bb.0: # %entry
+; SFB-NEXT: bnez a2, .LBB23_2
+; SFB-NEXT: # %bb.1: # %entry
+; SFB-NEXT: addiw a1, a0, 1234
+; SFB-NEXT: .LBB23_2: # %entry
+; SFB-NEXT: mv a0, a1
+; SFB-NEXT: ret
+entry:
+ %0 = add i32 %A, 1234
+ %1 = select i1 %cond, i32 %C, i32 %0
+ ret i32 %1
+}
+
+define i64 @select_addi(i64 %A, i64 %C, i1 zeroext %cond) {
+; NOSFB-LABEL: select_addi:
+; NOSFB: # %bb.0: # %entry
+; NOSFB-NEXT: bnez a2, .LBB24_2
+; NOSFB-NEXT: # %bb.1: # %entry
+; NOSFB-NEXT: addi a1, a0, 1234
+; NOSFB-NEXT: .LBB24_2: # %entry
+; NOSFB-NEXT: mv a0, a1
+; NOSFB-NEXT: ret
+;
+; SFB-LABEL: select_addi:
+; SFB: # %bb.0: # %entry
+; SFB-NEXT: bnez a2, .LBB24_2
+; SFB-NEXT: # %bb.1: # %entry
+; SFB-NEXT: addi a1, a0, 1234
+; SFB-NEXT: .LBB24_2: # %entry
+; SFB-NEXT: mv a0, a1
+; SFB-NEXT: ret
+entry:
+ %0 = add i64 %A, 1234
+ %1 = select i1 %cond, i64 %C, i64 %0
+ ret i64 %1
+}
+
+define i64 @select_andi(i64 %A, i64 %C, i1 zeroext %cond) {
+; NOSFB-LABEL: select_andi:
+; NOSFB: # %bb.0: # %entry
+; NOSFB-NEXT: bnez a2, .LBB25_2
+; NOSFB-NEXT: # %bb.1: # %entry
+; NOSFB-NEXT: andi a1, a0, 567
+; NOSFB-NEXT: .LBB25_2: # %entry
+; NOSFB-NEXT: mv a0, a1
+; NOSFB-NEXT: ret
+;
+; SFB-LABEL: select_andi:
+; SFB: # %bb.0: # %entry
+; SFB-NEXT: bnez a2, .LBB25_2
+; SFB-NEXT: # %bb.1: # %entry
+; SFB-NEXT: andi a1, a0, 567
+; SFB-NEXT: .LBB25_2: # %entry
+; SFB-NEXT: mv a0, a1
+; SFB-NEXT: ret
+entry:
+ %0 = and i64 %A, 567
+ %1 = select i1 %cond, i64 %C, i64 %0
+ ret i64 %1
+}
+
+define i64 @select_ori(i64 %A, i64 %C, i1 zeroext %cond) {
+; NOSFB-LABEL: select_ori:
+; NOSFB: # %bb.0: # %entry
+; NOSFB-NEXT: bnez a2, .LBB26_2
+; NOSFB-NEXT: # %bb.1: # %entry
+; NOSFB-NEXT: ori a1, a0, 890
+; NOSFB-NEXT: .LBB26_2: # %entry
+; NOSFB-NEXT: mv a0, a1
+; NOSFB-NEXT: ret
+;
+; SFB-LABEL: select_ori:
+; SFB: # %bb.0: # %entry
+; SFB-NEXT: bnez a2, .LBB26_2
+; SFB-NEXT: # %bb.1: # %entry
+; SFB-NEXT: ori a1, a0, 890
+; SFB-NEXT: .LBB26_2: # %entry
+; SFB-NEXT: mv a0, a1
+; SFB-NEXT: ret
+entry:
+ %0 = or i64 %A, 890
+ %1 = select i1 %cond, i64 %C, i64 %0
+ ret i64 %1
+}
+
+define i64 @select_xori(i64 %A, i64 %C, i1 zeroext %cond) {
+; NOSFB-LABEL: select_xori:
+; NOSFB: # %bb.0: # %entry
+; NOSFB-NEXT: bnez a2, .LBB27_2
+; NOSFB-NEXT: # %bb.1: # %entry
+; NOSFB-NEXT: xori a1, a0, 321
+; NOSFB-NEXT: .LBB27_2: # %entry
+; NOSFB-NEXT: mv a0, a1
+; NOSFB-NEXT: ret
+;
+; SFB-LABEL: select_xori:
+; SFB: # %bb.0: # %entry
+; SFB-NEXT: bnez a2, .LBB27_2
+; SFB-NEXT: # %bb.1: # %entry
+; SFB-NEXT: xori a1, a0, 321
+; SFB-NEXT: .LBB27_2: # %entry
+; SFB-NEXT: mv a0, a1
+; SFB-NEXT: ret
+entry:
+ %0 = xor i64 %A, 321
+ %1 = select i1 %cond, i64 %C, i64 %0
+ ret i64 %1
+}
+
+define i64 @select_slli(i64 %A, i64 %C, i1 zeroext %cond) {
+; NOSFB-LABEL: select_slli:
+; NOSFB: # %bb.0: # %entry
+; NOSFB-NEXT: bnez a2, .LBB28_2
+; NOSFB-NEXT: # %bb.1: # %entry
+; NOSFB-NEXT: slli a1, a0, 32
+; NOSFB-NEXT: .LBB28_2: # %entry
+; NOSFB-NEXT: mv a0, a1
+; NOSFB-NEXT: ret
+;
+; SFB-LABEL: select_slli:
+; SFB: # %bb.0: # %entry
+; SFB-NEXT: bnez a2, .LBB28_2
+; SFB-NEXT: # %bb.1: # %entry
+; SFB-NEXT: slli a1, a0, 32
+; SFB-NEXT: .LBB28_2: # %entry
+; SFB-NEXT: mv a0, a1
+; SFB-NEXT: ret
+entry:
+ %0 = shl i64 %A, 32
+ %1 = select i1 %cond, i64 %C, i64 %0
+ ret i64 %1
+}
+
+define i64 @select_srli(i64 %A, i64 %C, i1 zeroext %...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/66789
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