The Week Of Monday 19 February 2024 Archives by date
Starting: Mon Feb 19 00:02:38 PST 2024
Ending: Sun Feb 25 23:56:02 PST 2024
Messages: 4741
- [llvm] bb04909 - [gn build] Port 2ea5d167ae43
LLVM GN Syncbot via llvm-commits
- [llvm] [RISCV] Select pattern (shl (sext_vl/zext_vl), 1) to VWADD/VWADDU. (PR #82225)
Luke Lau via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Pierre van Houtryve via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Pierre van Houtryve via llvm-commits
- [clang] [llvm] [AMDGPU] Enable OpenCL hostcall printf (WIP) (PR #72556)
Vikram Hegde via llvm-commits
- [llvm] [DAGCombiner][RISCV] Optimize (zext nneg (truncate X)) if X has known sign bits. (PR #82227)
Craig Topper via llvm-commits
- [llvm] [DAGCombiner][RISCV] Optimize (zext nneg (truncate X)) if X has known sign bits. (PR #82227)
via llvm-commits
- [llvm] [GlobalISel] Constant-fold G_PTR_ADD with different type sizes (PR #81473)
Pierre van Houtryve via llvm-commits
- [llvm] [DAGCombiner][RISCV] Optimize (zext nneg (truncate X)) if X has known sign bits. (PR #82227)
via llvm-commits
- [clang] [llvm] [AMDGPU] Enable OpenCL hostcall printf (WIP) (PR #72556)
Vikram Hegde via llvm-commits
- [llvm] [llvm-readelf] Print ARM specific OSABI values in GNU mode (PR #82186)
James Henderson via llvm-commits
- [llvm] [MC/DC] Introduce `class TestVector` with a pair of `BitVector` (PR #82174)
NAKAMURA Takumi via llvm-commits
- [llvm] [MC/DC] Introduce `class TestVector` with a pair of `BitVector` (PR #82174)
NAKAMURA Takumi via llvm-commits
- [llvm] [MC/DC] Introduce `class TestVector` with a pair of `BitVector` (PR #82174)
NAKAMURA Takumi via llvm-commits
- [llvm] [MC/DC] Introduce `class TestVector` with a pair of `BitVector` (PR #82174)
NAKAMURA Takumi via llvm-commits
- [llvm] AMDGPU: Use HasFP8ConversionInsts appropriately, NFC (PR #82024)
Jay Foad via llvm-commits
- [llvm] [LLVM] Clang format cleanups. (PR #82184)
James Henderson via llvm-commits
- [compiler-rt] d043b4b - [Sanitizer][Windows] Fix Windows buildbot failure after 64790064e82467b43c04a70b6e9873e6939be81f (#82215)
via llvm-commits
- [compiler-rt] [Sanitizer][Windows] Fix Windows buildbot failure after 64790064e82467b43c04a70b6e9873e6939be81f (PR #82215)
via llvm-commits
- [llvm] [LangRef] Try to clarify some Metadata semantics (PR #81948)
Diana Picus via llvm-commits
- [llvm] [InstCombine] Don't require GEP in indexed compare fold (PR #81614)
Nikita Popov via llvm-commits
- [llvm] 442f066 - [AArch64AsmParser] Support (xxx), lsl 16 after #80571
Fangrui Song via llvm-commits
- [llvm] [llvm-exegesis] Simplify validation event string conversion functions (PR #82092)
Clement Courbet via llvm-commits
- [llvm] [Docs][llvm-exegesis] Add documentation on validation counters option (PR #82132)
Clement Courbet via llvm-commits
- [llvm] [llvm-exegesis] Add debug option to print per-measurement values (PR #81219)
Clement Courbet via llvm-commits
- [llvm] [llvm-exegesis] Add branch miss validation counter (PR #81094)
Clement Courbet via llvm-commits
- [llvm] [MC/DC] Introduce `class TestVector` with a pair of `BitVector` (PR #82174)
NAKAMURA Takumi via llvm-commits
- [llvm] 63dd08b - [llvm-exegesis] Add branch miss validation counter (#81094)
via llvm-commits
- [llvm] [llvm-exegesis] Add branch miss validation counter (PR #81094)
Aiden Grossman via llvm-commits
- [llvm] [llvm-exegesis] Add debug option to print per-measurement values (PR #81219)
Aiden Grossman via llvm-commits
- [llvm] [InstCombine] Do not perform binop-of-shuffle when mask is poison (PR #82185)
Antonio Frighetto via llvm-commits
- [llvm] [AArch64][GlobalISel] Refactor BITCAST Legalization (PR #80505)
David Green via llvm-commits
- [llvm] [SPIR-V] Fix vloadn OpenCL builtin lowering (PR #81148)
Nathan Gauër via llvm-commits
- [llvm] [SPIR-V] Fix vloadn OpenCL builtin lowering (PR #81148)
Nathan Gauër via llvm-commits
- [llvm] [SPIR-V] Fix vloadn OpenCL builtin lowering (PR #81148)
Nathan Gauër via llvm-commits
- [llvm] [llvm-exegesis] Add debug option to print per-measurement values (PR #81219)
Aiden Grossman via llvm-commits
- [llvm] 0c1f620 - [Docs][llvm-exegesis] Add documentation on validation counters option (#82132)
via llvm-commits
- [llvm] [Docs][llvm-exegesis] Add documentation on validation counters option (PR #82132)
Aiden Grossman via llvm-commits
- [llvm] 93db5b7 - [llvm-exegesis] Add debug option to print per-measurement values (#81219)
via llvm-commits
- [llvm] [llvm-exegesis] Add debug option to print per-measurement values (PR #81219)
Aiden Grossman via llvm-commits
- [llvm] [RISCV][MC] Implement ISA mapping symbols (PR #67541)
Joe Faulls via llvm-commits
- [llvm] [llvm-exegesis] Simplify validation event string conversion functions (PR #82092)
Aiden Grossman via llvm-commits
- [llvm] ad78e21 - [NFC][AArch64] Tests for guarding unrolling with scalable vec ins/ext (#81132)
via llvm-commits
- [llvm] [NFC][AArch64] Tests for guarding unrolling with scalable vec ins/ext (PR #81132)
Graham Hunter via llvm-commits
- [llvm] [AArch64] Improve cost model for legal subvec insert/extract (PR #81135)
Graham Hunter via llvm-commits
- [llvm] [CodeGenPrepare] Reverse the canonicalization of isInf/isNanOrInf (PR #81572)
Yingwei Zheng via llvm-commits
- [llvm] [RemoveDIs] Print non-intrinsic debug info in textual IR output (PR #79281)
Stephen Tozer via llvm-commits
- [llvm] [RemoveDIs] Print non-intrinsic debug info in textual IR output (PR #79281)
Stephen Tozer via llvm-commits
- [llvm] [RemoveDIs] Print non-intrinsic debug info in textual IR output (PR #79281)
via llvm-commits
- [llvm] fix generation of unnecessary OpExecutionMode records (PR #81839)
Nathan Gauër via llvm-commits
- [llvm] [InstCombine] Don't require GEP in indexed compare fold (PR #81614)
Yingwei Zheng via llvm-commits
- [llvm] [InstCombine] Fix Failure to fold (and %x, (sext i1 %m)) -> (select %m, %x, 0) with multiple uses of %m (PR #81409)
Nikita Popov via llvm-commits
- [llvm] 4b483ec - [InstCombine] Fix failure to fold (and %x, (sext i1 %m)) -> (select %m, %x, 0) with multiple uses of %m (#81409)
via llvm-commits
- [llvm] [InstCombine] Fix Failure to fold (and %x, (sext i1 %m)) -> (select %m, %x, 0) with multiple uses of %m (PR #81409)
Nikita Popov via llvm-commits
- [llvm] [InstCombine] Fix Failure to fold (and %x, (sext i1 %m)) -> (select %m, %x, 0) with multiple uses of %m (PR #81409)
via llvm-commits
- [llvm] [mlir] [OpenMP][MLIR][OMPIRBuilder] Add a small optional constant alloca raise function pass to finalize, utilised in convertTarget (PR #78818)
Kiran Chandramohan via llvm-commits
- [clang] [llvm] [AMDGPU] Enable OpenCL hostcall printf (WIP) (PR #72556)
Vikram Hegde via llvm-commits
- [llvm] [DAGCombiner] Preserve nneg flag from inner zext when we combine (z/s/aext (zext X)) (PR #82199)
Nikita Popov via llvm-commits
- [llvm] fix generation of unnecessary OpExecutionMode records (PR #81839)
Vyacheslav Levytskyy via llvm-commits
- [llvm] [MergeFunctions] Fix thunks for non-instruction debug info (PR #82080)
Jeremy Morse via llvm-commits
- [llvm] [InstCombine] If inst in unreachable refers to an inst change it to poison (#65107) (PR #78444)
via llvm-commits
- [llvm] 0215d2c - arm64_32: extend @llvm.stackguard call to in-DAG 64-bits before handing off
Tim Northover via llvm-commits
- [llvm] arm64_32: extend @llvm.stackguard call to in-DAG 64-bits before handing off (PR #77318)
Tim Northover via llvm-commits
- [llvm] arm64_32: extend @llvm.stackguard call to in-DAG 64-bits before handing off (PR #77318)
Tim Northover via llvm-commits
- [llvm] [AMDGPU] Stop using SDWA DecoderNamespaces. NFCI. (PR #82233)
Jay Foad via llvm-commits
- [llvm] [AMDGPU] Stop using SDWA DecoderNamespaces. NFCI. (PR #82233)
via llvm-commits
- [llvm] [InstCombine] If inst in unreachable refers to an inst change it to poison (#65107) (PR #78444)
Nikita Popov via llvm-commits
- [llvm] [AMDGPU] Stop using SDWA DecoderNamespaces. NFCI. (PR #82233)
Jay Foad via llvm-commits
- [llvm] 232a14d - [BatchAA] Fix a reference to a non-exising `pointsToConstantMemory` overload (NFC) (#82173)
via llvm-commits
- [llvm] [BatchAA] Fix a reference to a non-exising `pointsToConstantMemory` overload (NFC) (PR #82173)
Momchil Velikov via llvm-commits
- [llvm] 658e476 - [AArch64] Fix wrong condition in `canUseAsPrologue` (#81878)
via llvm-commits
- [llvm] [AArch64] Fix wrong condition in `canUseAsPrologue` (PR #81878)
Momchil Velikov via llvm-commits
- [clang] [libc] [llvm] [openmp] [libc] Rework the GPU build to be a regular target (PR #81921)
Jan Patrick Lehr via llvm-commits
- [clang] [libc] [llvm] [openmp] [libc] Rework the GPU build to be a regular target (PR #81921)
Jan Patrick Lehr via llvm-commits
- [clang] [libc] [llvm] [openmp] [libc] Rework the GPU build to be a regular target (PR #81921)
Jan Patrick Lehr via llvm-commits
- [llvm] [VPlan] Consistently use (Part, 0) for first lane scalar values (PR #80271)
Florian Hahn via llvm-commits
- [llvm] [DAGCombiner][RISCV] Optimize (zext nneg (truncate X)) if X has known sign bits. (PR #82227)
Nikita Popov via llvm-commits
- [llvm] 69d4890 - [InstCombine] Fold abs(a * abs(b)) --> abs(a * b) (#78110)
via llvm-commits
- [llvm] [InstCombine] Fold abs(a * abs(b)) --> abs(a * b) (PR #78110)
Nikita Popov via llvm-commits
- [llvm] [LoopPeel] LCSSA form is destroyed by LoopPeel, preserve it (PR #78696)
Nikita Popov via llvm-commits
- [llvm] [VectorCombine] Fold reduce(trunc(x)) -> trunc(reduce(x)) iff cost effective (PR #81852)
Nikita Popov via llvm-commits
- [llvm] [VectorCombine] Fold reduce(trunc(x)) -> trunc(reduce(x)) iff cost effective (PR #81852)
Nikita Popov via llvm-commits
- [llvm] [LICM] Fold associative binary ops to promote code hoisting (PR #81608)
Ricardo Jesus via llvm-commits
- [llvm] [LICM] Fold associative binary ops to promote code hoisting (PR #81608)
Ricardo Jesus via llvm-commits
- [llvm] 925768e - Add support for atomic instruction on floating-point numbers (#81683)
via llvm-commits
- [llvm] Add support for atomic instruction on floating-point numbers (PR #81683)
Vyacheslav Levytskyy via llvm-commits
- [llvm] [VectorCombine] Fold reduce(trunc(x)) -> trunc(reduce(x)) iff cost effective (PR #81852)
Simon Pilgrim via llvm-commits
- [llvm] [VectorCombine] Fold reduce(trunc(x)) -> trunc(reduce(x)) iff cost effective (PR #81852)
Simon Pilgrim via llvm-commits
- [llvm] [VectorCombine] Fold reduce(trunc(x)) -> trunc(reduce(x)) iff cost effective (PR #81852)
Simon Pilgrim via llvm-commits
- [llvm] [RemoveDIs][DebugInfo] Check for null marker when printing DPValues (PR #82238)
Stephen Tozer via llvm-commits
- [llvm] [RemoveDIs][DebugInfo] Check for null marker when printing DPValues (PR #82238)
via llvm-commits
- [llvm] [RemoveDIs][DebugInfo] Check for null marker when printing DPValues (PR #82238)
Stephen Tozer via llvm-commits
- [llvm] 769c22f - [VectorCombine] Fold reduce(trunc(x)) -> trunc(reduce(x)) iff cost effective (#81852)
via llvm-commits
- [llvm] [VectorCombine] Fold reduce(trunc(x)) -> trunc(reduce(x)) iff cost effective (PR #81852)
Simon Pilgrim via llvm-commits
- [llvm] [RemoveDIs][DebugInfo] Check for null marker when printing DPValues (PR #82238)
Orlando Cazalet-Hyams via llvm-commits
- [llvm] 5b342e6 - [RemoveDIs][DebugInfo] Check for null marker when printing DPValues (#82238)
via llvm-commits
- [llvm] [RemoveDIs][DebugInfo] Check for null marker when printing DPValues (PR #82238)
Stephen Tozer via llvm-commits
- [llvm] [AArch64][CodeGen] Fix crash when fptrunc returns fp16 with +nofp attr (PR #81724)
Nashe Mncube via llvm-commits
- [llvm] [AArch64] Restore Z-registers before P-registers (PR #79623)
via llvm-commits
- [llvm] [AMDGPU] Prevent cyclic behaviour in SIFoldOperands (PR #82099)
Jay Foad via llvm-commits
- [llvm] [AArch64] Restore Z-registers before P-registers (PR #79623)
Momchil Velikov via llvm-commits
- [lld] [llvm] Support for Missing Line Numbers. (PR #82240)
via llvm-commits
- [lld] [llvm] Support for Missing Line Numbers. (PR #82240)
via llvm-commits
- [lld] [llvm] Support for Missing Line Numbers. (PR #82240)
via llvm-commits
- [llvm] [LLVM][IR] Add native vector support to ConstantInt & ConstantFP. (PR #74502)
Nikita Popov via llvm-commits
- [llvm] [LLVM][IR] Add native vector support to ConstantInt & ConstantFP. (PR #74502)
Nikita Popov via llvm-commits
- [llvm] [LLVM][IR] Add native vector support to ConstantInt & ConstantFP. (PR #74502)
Nikita Popov via llvm-commits
- [llvm] [VPlan] Consistently use (Part, 0) for first lane scalar values (PR #80271)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Consistently use (Part, 0) for first lane scalar values (PR #80271)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Consistently use (Part, 0) for first lane scalar values (PR #80271)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Consistently use (Part, 0) for first lane scalar values (PR #80271)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Consistently use (Part, 0) for first lane scalar values (PR #80271)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Consistently use (Part, 0) for first lane scalar values (PR #80271)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Consistently use (Part, 0) for first lane scalar values (PR #80271)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Consistently use (Part, 0) for first lane scalar values (PR #80271)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Consistently use (Part, 0) for first lane scalar values (PR #80271)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Consistently use (Part, 0) for first lane scalar values (PR #80271)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Consistently use (Part, 0) for first lane scalar values (PR #80271)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Consistently use (Part, 0) for first lane scalar values (PR #80271)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Consistently use (Part, 0) for first lane scalar values (PR #80271)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Consistently use (Part, 0) for first lane scalar values (PR #80271)
Florian Hahn via llvm-commits
- [lld] [llvm] Support for Missing Line Numbers. (PR #82240)
via llvm-commits
- [llvm] [LLVM][SelectionDAG] Reduce number of ComputeValueVTs variants. (PR #75614)
Sander de Smalen via llvm-commits
- [llvm] [VPlan] Consistently use (Part, 0) for first lane scalar values (PR #80271)
Florian Hahn via llvm-commits
- [llvm] d022f32 - Revert "[ARM] __ARM_ARCH macro definition fix (#81493)"
Tomas Matheson via llvm-commits
- [lld] [llvm] Support for Missing Line Numbers. (PR #82240)
James Henderson via llvm-commits
- [llvm] [MachineLICM][AArch64] Hoist COPY instructions with other uses in the loop (PR #71403)
via llvm-commits
- [lld] [llvm] Support for Missing Line Numbers. (PR #82240)
via llvm-commits
- [llvm] [MachineLICM] Hoist COPY instruction only when user can be hoisted (PR #81735)
via llvm-commits
- [lld] [llvm] Support for Missing Line Numbers. (PR #82240)
James Henderson via llvm-commits
- [lld] [llvm] Support for Missing Line Numbers. (PR #82240)
via llvm-commits
- [llvm] [Symbolizer] Compute Nearest Line Info for Address. (PR #71032)
via llvm-commits
- [llvm] [Symbolizer] Compute Nearest Line Info for Address. (PR #71032)
via llvm-commits
- [llvm] [LLVM][IR] Add native vector support to ConstantInt & ConstantFP. (PR #74502)
Nikita Popov via llvm-commits
- [llvm] [Release] Don't build during test-release.sh Phase 3 install (PR #82001)
Rainer Orth via llvm-commits
- [llvm] [CodeGen] Port AtomicExpand to new Pass Manager (PR #71220)
via llvm-commits
- [llvm] [NewPM/CodeGen] Rewrite pass manager nesting (PR #81068)
via llvm-commits
- [llvm] [NewPM/CodeGen] Rewrite pass manager nesting (PR #81068)
via llvm-commits
- [llvm] [NewPM/CodeGen] Rewrite pass manager nesting (PR #81068)
via llvm-commits
- [llvm] [NewPM/CodeGen] Rewrite pass manager nesting (PR #81068)
via llvm-commits
- [llvm] [AMDGPU][NFC] Extend PredicateControl to support True16 predicates. (PR #82245)
Ivan Kosarev via llvm-commits
- [llvm] [AMDGPU][NFC] Extend PredicateControl to support True16 predicates. (PR #82245)
via llvm-commits
- [llvm] AMDGPU: Use HasFP8ConversionInsts appropriately, NFC (PR #82024)
Ivan Kosarev via llvm-commits
- [llvm] [AMDGPU][NFC] Extend PredicateControl to support True16 predicates. (PR #82245)
Jay Foad via llvm-commits
- [llvm] [LangRef] Clarify definition of fragments and debug intrinsics (PR #82019)
Stephen Tozer via llvm-commits
- [llvm] [LangRef] Clarify definition of fragments and debug intrinsics (PR #82019)
Stephen Tozer via llvm-commits
- [llvm] Add support for the SPV_INTEL_usm_storage_classes extension (PR #82247)
Vyacheslav Levytskyy via llvm-commits
- [llvm] Initialize unsigned integer when declared (PR #81894)
Martin Wehking via llvm-commits
- [llvm] Add support for the SPV_INTEL_usm_storage_classes extension (PR #82247)
via llvm-commits
- [llvm] Add support for the SPV_INTEL_usm_storage_classes extension (PR #82247)
Vyacheslav Levytskyy via llvm-commits
- [llvm] 3f0404a - [AArch64] Restore Z-registers before P-registers (#79623)
via llvm-commits
- [llvm] [AArch64] Restore Z-registers before P-registers (PR #79623)
via llvm-commits
- [llvm] [InstCombine] If inst in unreachable refers to an inst change it to poison (#65107) (PR #78444)
via llvm-commits
- [llvm] Initialize unsigned integer when declared (PR #81894)
Martin Wehking via llvm-commits
- [llvm] Initialize unsigned integer when declared (PR #81894)
via llvm-commits
- [llvm] [mlir] Add missing dialects to C API (PR #82190)
Sergio Sánchez Ramírez via llvm-commits
- [llvm] Add support for the SPV_INTEL_usm_storage_classes extension (PR #82247)
Vyacheslav Levytskyy via llvm-commits
- [llvm] Add support for the SPV_INTEL_usm_storage_classes extension (PR #82247)
Vyacheslav Levytskyy via llvm-commits
- [llvm] Add support for the SPV_INTEL_usm_storage_classes extension (PR #82247)
via llvm-commits
- [llvm] [RemoveDIs][DebugInfo][IR] Add parsing for non-intrinsic debug values (PR #79818)
Stephen Tozer via llvm-commits
- [llvm] [llvm-exegesis] Simplify validation event string conversion functions (PR #82092)
Clement Courbet via llvm-commits
- [llvm] [RemoveDIs][DebugInfo][IR] Add parsing for non-intrinsic debug values (PR #79818)
Stephen Tozer via llvm-commits
- [llvm] [AArch64] Improve cost model for legal subvec insert/extract (PR #81135)
Graham Hunter via llvm-commits
- [llvm] [AArch64] Improve cost model for legal subvec insert/extract (PR #81135)
Graham Hunter via llvm-commits
- [llvm] [AArch64] Improve cost model for legal subvec insert/extract (PR #81135)
Graham Hunter via llvm-commits
- [llvm] [AArch64] Improve cost model for legal subvec insert/extract (PR #81135)
Graham Hunter via llvm-commits
- [llvm] [AArch64] Added feature dependencies for SME2p1 to TargetParser (PR #81860)
via llvm-commits
- [clang] [libc] [llvm] [openmp] [libc] Rework the GPU build to be a regular target (PR #81921)
Joseph Huber via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Janek van Oirschot via llvm-commits
- [llvm] [AArch64][SVE] Add intrinsincs to assembly mapping for svpmov (PR #81861)
via llvm-commits
- [llvm] [LLVM][AArch64]Use load/store with consecutive registers in SME2 or S… (PR #77665)
via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Janek van Oirschot via llvm-commits
- [llvm] [AArch64] Added feature dependencies for SME2p1 to TargetParser (PR #81860)
via llvm-commits
- [llvm] [AMDGPU] Add AMDGPU specific variadic operation MCExprs (PR #82022)
Janek van Oirschot via llvm-commits
- [llvm] [AArch64][SVE] Add intrinsincs to assembly mapping for svpmov (PR #81861)
via llvm-commits
- [llvm] [Lint] Add option --lint-abort-on-error (PR #81999)
Sebastian Neubauer via llvm-commits
- [llvm] [NFC][SelectionDAG] Move function `getStackAlignedMMO` to the beginning of LegalizeDAG.cpp (PR #82171)
Manish Kausik H via llvm-commits
- [llvm] [AArch64] Improve cost model for legal subvec insert/extract (PR #81135)
Graham Hunter via llvm-commits
- [llvm] [NFC][SelectionDAG] Move function `getStackAlignedMMO` to the beginning of LegalizeDAG.cpp (PR #82171)
Manish Kausik H via llvm-commits
- [llvm] 652081c - [NFC][SelectionDAG] Move function `getStackAlignedMMO` to the beginning of LegalizeDAG.cpp (#82171)
via llvm-commits
- [llvm] [NFC][SelectionDAG] Move function `getStackAlignedMMO` to the beginning of LegalizeDAG.cpp (PR #82171)
Danila Malyutin via llvm-commits
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Florian Hahn via llvm-commits
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Florian Hahn via llvm-commits
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Florian Hahn via llvm-commits
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Florian Hahn via llvm-commits
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Artem Tyurin via llvm-commits
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Craig Topper via llvm-commits
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Craig Topper via llvm-commits
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Craig Topper via llvm-commits
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Yeting Kuo via llvm-commits
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Yeting Kuo via llvm-commits
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Yeting Kuo via llvm-commits
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Yeting Kuo via llvm-commits
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Yeting Kuo via llvm-commits
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Yeting Kuo via llvm-commits
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Craig Topper via llvm-commits
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Yeting Kuo via llvm-commits
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Sam Clegg via llvm-commits
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Sam Clegg via llvm-commits
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Sam Clegg via llvm-commits
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Sam Clegg via llvm-commits
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Chen Zheng via llvm-commits
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James Henderson via llvm-commits
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- [llvm] [InstCombine] Fold (sub (xor X, (sext C)), (sext C)) => (select C (neg X), X) (PR #79417)
Kai Luo via llvm-commits
- [llvm] [X86] Try Folding icmp of v8i32 -> fcmp of v8f32 on AVX (PR #82290)
Phoebe Wang via llvm-commits
- [llvm] [PowerPC] Do not generate `isel` instruction if target doesn't have this instruction (PR #72845)
Kai Luo via llvm-commits
- [llvm] Reapply [workflows] Split pr-code-format into two parts to make it more secure (#78215) (PR #80495)
James Y Knight via llvm-commits
- [llvm] Reapply [workflows] Split pr-code-format into two parts to make it more secure (#78215) (PR #80495)
James Y Knight via llvm-commits
- [llvm] Reapply [workflows] Split pr-code-format into two parts to make it more secure (#78215) (PR #80495)
James Y Knight via llvm-commits
- [llvm] [asan] Disable instrumentation for available_externally global with COFF (PR #81109)
Wu Yingcong via llvm-commits
- [llvm] [BOLT] Fix runtime/instrument-wrong-target.s test (PR #82858)
Davide Italiano via llvm-commits
- [llvm] [BOLT] Fix runtime/instrument-wrong-target.s test (PR #82858)
Davide Italiano via llvm-commits
- [llvm] [llvm][Support] Add support for executing a detached process (PR #81708)
Connor Sughrue via llvm-commits
- [llvm] [llvm][Support] Add support for executing a detached process (PR #81708)
via llvm-commits
- [llvm] [llvm][Support] Add support for executing a detached process (PR #81708)
Connor Sughrue via llvm-commits
- [llvm] Introduce mcdc::TVIdxBuilder (LLVM side, NFC) (PR #80676)
Jessica Paquette via llvm-commits
- [llvm] [MC/DC] Refactor: Isolate the final result out of TestVectors (PR #82282)
Jessica Paquette via llvm-commits
- [llvm] 8be39b3 - [LoongArch] Improve pattern matching for AddLike predicate (#82767)
via llvm-commits
- [llvm] [LoongArch] Improve pattern matching for AddLike predicate (PR #82767)
via llvm-commits
- [llvm] [Tests][LoopDistribute] Re-adding target triple in a test that was removed earlier to fix build errors (PR #82954)
Nilanjana Basu via llvm-commits
- [llvm] [Tests][LoopDistribute] Re-adding target triple in a test that was removed earlier to fix build errors (PR #82954)
via llvm-commits
- [llvm] [LV] Removing option that is no longer needed after recent updates to loop interleaving algorithm (PR #82955)
Nilanjana Basu via llvm-commits
- [llvm] [LV] Removing option that is no longer needed after recent updates to loop interleaving algorithm (PR #82955)
via llvm-commits
- [lld] [llvm] [Symbolizer] Support for Missing Line Numbers. (PR #82240)
via llvm-commits
- [llvm] c087beb - Introduce mcdc::TVIdxBuilder (LLVM side, NFC) (#80676)
via llvm-commits
- [llvm] Introduce mcdc::TVIdxBuilder (LLVM side, NFC) (PR #80676)
NAKAMURA Takumi via llvm-commits
- [lld] Improve readability of "undefined reference" message (PR #82671)
David Blaikie via llvm-commits
- [llvm] [TableGen] Efficiency improvements for encoding HwMode collection. (PR #82902)
Wang Pengcheng via llvm-commits
- [llvm] [mlir] Split the llvm::ThreadPool into an abstract base class and an implementation (PR #82094)
Mehdi Amini via llvm-commits
- [llvm] [mlir] Split the llvm::ThreadPool into an abstract base class and an implementation (PR #82094)
Mehdi Amini via llvm-commits
- [llvm] [mlir] Split the llvm::ThreadPool into an abstract base class and an implementation (PR #82094)
Mehdi Amini via llvm-commits
- [llvm] [mlir] Split the llvm::ThreadPool into an abstract base class and an implementation (PR #82094)
Mehdi Amini via llvm-commits
- [llvm] [TableGen] Efficiency improvements for encoding HwMode collection. (PR #82902)
Jason Eckhardt via llvm-commits
- [llvm] f75c6ed - [TableGen] Efficiency improvements for encoding HwMode collection. (#82902)
via llvm-commits
- [llvm] [TableGen] Efficiency improvements for encoding HwMode collection. (PR #82902)
Wang Pengcheng via llvm-commits
- [llvm] [llvm-ar][Object] Use K_GNU instead of K_COFF for archives with no symtab. (PR #82898)
Eli Friedman via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Wang Pengcheng via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Wang Pengcheng via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Wang Pengcheng via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Wang Pengcheng via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Wang Pengcheng via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Wang Pengcheng via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Wang Pengcheng via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Wang Pengcheng via llvm-commits
- [llvm] [mlir] Split the llvm::ThreadPool into an abstract base class and an implementation (PR #82094)
Mehdi Amini via llvm-commits
- [llvm] [mlir] Split the llvm::ThreadPool into an abstract base class and an implementation (PR #82094)
Mehdi Amini via llvm-commits
- [clang] [llvm] [AMDGPU] Enable OpenCL hostcall printf (WIP) (PR #72556)
Sameer Sahasrabuddhe via llvm-commits
- [llvm] [X86] Try Folding icmp of v8i32 -> fcmp of v8f32 on AVX (PR #82290)
via llvm-commits
- [llvm] [AArch64][GlobalISel] Improve codegen for G_VECREDUCE_{SMIN,SMAX,UMIN,UMAX} for odd-sized vectors (PR #82740)
Dhruv Chawla via llvm-commits
- [llvm] [docs] Remove the Packaging "Tips" which seems to be about pre-cmake ./configure (PR #82958)
Mehdi Amini via llvm-commits
- [llvm] [VP][RISCV] Introduce vp.lrint/llrint and RISC-V support. (PR #82627)
Luke Lau via llvm-commits
- [llvm] [PowerPC] Do not generate `isel` instruction if target doesn't have this instruction (PR #72845)
Chen Zheng via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Craig Topper via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Craig Topper via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Craig Topper via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Craig Topper via llvm-commits
- [llvm] [X86] Try Folding icmp of v8i32 -> fcmp of v8f32 on AVX (PR #82290)
Timothy Herchen via llvm-commits
- [llvm] [RISCV][MC] Implement ISA mapping symbols (PR #67541)
Craig Topper via llvm-commits
- [llvm] [RISCV][MC] Implement ISA mapping symbols (PR #67541)
Craig Topper via llvm-commits
- [llvm] [X86] Try Folding icmp of v8i32 -> fcmp of v8f32 on AVX (PR #82290)
via llvm-commits
- [compiler-rt] [llvm] A copy of https://github.com/llvm/llvm-project/pull/66825. Actually this is a superset (a copy plus the thinlto-import change) (PR #80761)
Mingming Liu via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Wang Pengcheng via llvm-commits
- [llvm] [RISCV] RISCV vector calling convention (2/2) (PR #79096)
Brandon Wu via llvm-commits
- [llvm] [RISCV] RISCV vector calling convention (2/2) (PR #79096)
Brandon Wu via llvm-commits
- [llvm] [X86] Try Folding icmp of v8i32 -> fcmp of v8f32 on AVX (PR #82290)
Timothy Herchen via llvm-commits
- [llvm] [llvm-exegesis] Remove exegesis prefix in exegesis namespace (PR #82871)
Clement Courbet via llvm-commits
- [llvm] [GVN] Drop nsw/nuw flags when replacing the result of a with.overflow intrinsic with a overflowing binary operator (PR #82935)
Nikita Popov via llvm-commits
- [llvm] 16d0592 - [llvm-exegesis] Remove exegesis prefix in exegesis namespace (#82871)
via llvm-commits
- [llvm] [llvm-exegesis] Remove exegesis prefix in exegesis namespace (PR #82871)
Aiden Grossman via llvm-commits
- [llvm] [llvm-exegesis] Add loop-register snippet annotation (PR #82873)
Clement Courbet via llvm-commits
- [llvm] [llvm-exegesis] Add loop-register snippet annotation (PR #82873)
Clement Courbet via llvm-commits
- [llvm] [llvm-exegesis] Add loop-register snippet annotation (PR #82873)
Clement Courbet via llvm-commits
- [llvm] [X86][MC] Teach disassembler to recognize apx instructions which ignores W bit (PR #82747)
Shengchen Kan via llvm-commits
- [llvm] [VP][RISCV] Introduce vp.lrint/llrint and RISC-V support. (PR #82627)
Yeting Kuo via llvm-commits
- [llvm] [VP][RISCV] Introduce vp.lrint/llrint and RISC-V support. (PR #82627)
Yeting Kuo via llvm-commits
- [llvm] [VPlan] Delay adding canonical IV increment and exit branches. (PR #82270)
Florian Hahn via llvm-commits
- [llvm] [RISCV][NFC] Use sub to construct RVV registers without V0 (PR #82962)
Wang Pengcheng via llvm-commits
- [llvm] [RISCV][NFC] Use sub to construct RVV registers without V0 (PR #82962)
via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Brendan Sweeney via llvm-commits
- [llvm] [VP][RISCV] Introduce vp.lrint/llrint and RISC-V support. (PR #82627)
Luke Lau via llvm-commits
- [llvm] [PPC] adjust cost for extract i64 from vector on P9 and above (PR #82963)
Chen Zheng via llvm-commits
- [llvm] [PPC] adjust cost for extract i64 from vector on P9 and above (PR #82963)
via llvm-commits
- [llvm] [PowerPC] adjust cost for extract i64 from vector on P9 and above (PR #82963)
Chen Zheng via llvm-commits
- [llvm] [X86] Try Folding icmp of v8i32 -> fcmp of v8f32 on AVX (PR #82290)
via llvm-commits
- [llvm] [LICM] Fold associative binary ops to promote code hoisting (PR #81608)
Ricardo Jesus via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Brendan Sweeney via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Brendan Sweeney via llvm-commits
- [llvm] [X86] Try Folding icmp of v8i32 -> fcmp of v8f32 on AVX (PR #82290)
Timothy Herchen via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Brendan Sweeney via llvm-commits
- [llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)
Brendan Sweeney via llvm-commits
- [llvm] 892b4be - [GVN] Drop nsw/nuw flags when replacing the result of a with.overflow intrinsic with a overflowing binary operator (#82935)
via llvm-commits
- [llvm] [GVN] Drop nsw/nuw flags when replacing the result of a with.overflow intrinsic with a overflowing binary operator (PR #82935)
Yingwei Zheng via llvm-commits
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Archived on: Sun Feb 25 23:56:07 PST 2024
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