[llvm] [LoongArch] Improve pattern matching for AddLike predicate (PR #82767)

[via llvm-commits]

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@@ -4214,7 +4214,7 @@ bool SelectionDAGISel::isOrEquivalentToAdd(const SDNode *N) const {
     // the alignment, then this or is really an add.
     return (Off >= 0) && (((A.value() - 1) & Off) == unsigned(Off));
   }
-  return false;
+  return CurDAG->haveNoCommonBitsSet(N->getOperand(0), N->getOperand(1));
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heiher wrote:

Thanks. :+1: 

https://github.com/llvm/llvm-project/pull/82767