[llvm] [Mips] mips1 DivByZeroTrap (PR #81311)

[via llvm-commits]

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@@ -202,21 +258,55 @@ entry:
 }
 
 define signext i64 @udiv_i64(i64 signext %a, i64 signext %b) {
-; GP32-LABEL: udiv_i64:
-; GP32:       # %bb.0: # %entry
-; GP32-NEXT:    lui $2, %hi(_gp_disp)
-; GP32-NEXT:    addiu $2, $2, %lo(_gp_disp)
-; GP32-NEXT:    addiu $sp, $sp, -24
-; GP32-NEXT:    .cfi_def_cfa_offset 24
-; GP32-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
-; GP32-NEXT:    .cfi_offset 31, -4
-; GP32-NEXT:    addu $gp, $2, $25
-; GP32-NEXT:    lw $25, %call16(__udivdi3)($gp)
-; GP32-NEXT:    jalr $25
-; GP32-NEXT:    nop
-; GP32-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
-; GP32-NEXT:    jr $ra
-; GP32-NEXT:    addiu $sp, $sp, 24
+; GP32R0R1-LABEL: udiv_i64:
+; GP32R0R1:       # %bb.0: # %entry
+; GP32R0R1-NEXT:    lui $2, %hi(_gp_disp)
+; GP32R0R1-NEXT:    addiu $2, $2, %lo(_gp_disp)
+; GP32R0R1-NEXT:    addiu $sp, $sp, -24
+; GP32R0R1-NEXT:    .cfi_def_cfa_offset 24
+; GP32R0R1-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; GP32R0R1-NEXT:    .cfi_offset 31, -4
+; GP32R0R1-NEXT:    addu $gp, $2, $25
+; GP32R0R1-NEXT:    lw $25, %call16(__udivdi3)($gp)
+; GP32R0R1-NEXT:    nop
+; GP32R0R1-NEXT:    jalr $25
+; GP32R0R1-NEXT:    nop
+; GP32R0R1-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; GP32R0R1-NEXT:    nop
+; GP32R0R1-NEXT:    jr $ra
+; GP32R0R1-NEXT:    addiu $sp, $sp, 24
+;
+; GP32R0R2-LABEL: udiv_i64:
+; GP32R0R2:       # %bb.0: # %entry
+; GP32R0R2-NEXT:    lui $2, %hi(_gp_disp)
+; GP32R0R2-NEXT:    addiu $2, $2, %lo(_gp_disp)
+; GP32R0R2-NEXT:    addiu $sp, $sp, -24
+; GP32R0R2-NEXT:    .cfi_def_cfa_offset 24
+; GP32R0R2-NEXT:    sw $ra, 20($sp) # 4-byte Folded Spill
+; GP32R0R2-NEXT:    .cfi_offset 31, -4
+; GP32R0R2-NEXT:    addu $gp, $2, $25
+; GP32R0R2-NEXT:    lw $25, %call16(__udivdi3)($gp)
+; GP32R0R2-NEXT:    jalr $25
+; GP32R0R2-NEXT:    nop
+; GP32R0R2-NEXT:    lw $ra, 20($sp) # 4-byte Folded Reload
+; GP32R0R2-NEXT:    jr $ra
+; GP32R0R2-NEXT:    addiu $sp, $sp, 24
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cmccord-dev wrote:

The nop is at least significant on mips1 since it has load delay slots, removing it would not be valid, but I agree that this test case is kind of pointless otherwise.  or is there some way of merging it and keeping the nop only for mips1?

https://github.com/llvm/llvm-project/pull/81311