[llvm] [Sparc] Use generated MatchRegisterName (NFCI) (PR #82165)

[Sergei Barannikov via llvm-commits]

================
@@ -1325,314 +1295,131 @@ ParseStatus SparcAsmParser::parseBranchModifiers(OperandVector &Operands) {
   return ParseStatus::Success;
 }
 
-bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, MCRegister &RegNo,
-                                       unsigned &RegKind) {
-  int64_t intVal = 0;
-  RegNo = 0;
-  RegKind = SparcOperand::rk_None;
-  if (Tok.is(AsmToken::Identifier)) {
-    StringRef name = Tok.getString();
-
-    // %fp
-    if (name.equals("fp")) {
-      RegNo = Sparc::I6;
-      RegKind = SparcOperand::rk_IntReg;
-      return true;
-    }
-    // %sp
-    if (name.equals("sp")) {
-      RegNo = Sparc::O6;
-      RegKind = SparcOperand::rk_IntReg;
-      return true;
-    }
-
-    if (name.equals("y")) {
-      RegNo = Sparc::Y;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
+#define GET_REGISTER_MATCHER
+#include "SparcGenAsmMatcher.inc"
 
-    if (name.starts_with_insensitive("asr") &&
-        !name.substr(3).getAsInteger(10, intVal) && intVal > 0 && intVal < 32) {
-      RegNo = ASRRegs[intVal];
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
+MCRegister SparcAsmParser::matchRegisterName(const AsmToken &Tok,
+                                             unsigned &RegKind) {
+  RegKind = SparcOperand::rk_None;
+  if (!Tok.is(AsmToken::Identifier))
+    return SP::NoRegister;
 
-    if (name.equals("fprs")) {
-      RegNo = Sparc::ASR6;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
+  StringRef Name = Tok.getString();
+  MCRegister Reg = MatchRegisterName(Name.lower());
+  if (!Reg)
+    Reg = MatchRegisterAltName(Name.lower());
 
-    if (name.equals("icc")) {
-      RegNo = Sparc::ICC;
-      RegKind = SparcOperand::rk_Special;
-      return true;
-    }
+  if (Reg) {
+    // Some registers have identical spellings. The generated matcher might
+    // have chosen one or another spelling, e.g. "%fp" or "%i6" might have been
+    // matched to either SP::I6 or SP::I6_I7. Other parts of SparcAsmParser
+    // are not prepared for this, so we do some canonicalization.
 
-    if (name.equals("psr")) {
-      RegNo = Sparc::PSR;
+    // See the note in SparcRegisterInfo.td near ASRRegs register class.
+    if (Reg == SP::ASR4 && Name == "tick") {
       RegKind = SparcOperand::rk_Special;
-      return true;
+      return SP::TICK;
     }
 
-    if (name.equals("fsr")) {
-      RegNo = Sparc::FSR;
-      RegKind = SparcOperand::rk_Special;
-      return true;
+    if (MRI.getRegClass(SP::IntRegsRegClassID).contains(Reg)) {
+      RegKind = SparcOperand::rk_IntReg;
+      return Reg;
     }
-
-    if (name.equals("fq")) {
-      RegNo = Sparc::FQ;
-      RegKind = SparcOperand::rk_Special;
-      return true;
+    if (MRI.getRegClass(SP::FPRegsRegClassID).contains(Reg)) {
+      RegKind = SparcOperand::rk_FloatReg;
+      return Reg;
     }
-
-    if (name.equals("csr")) {
-      RegNo = Sparc::CPSR;
-      RegKind = SparcOperand::rk_Special;
-      return true;
+    if (MRI.getRegClass(SP::CoprocRegsRegClassID).contains(Reg)) {
+      RegKind = SparcOperand::rk_CoprocReg;
+      return Reg;
     }
 
-    if (name.equals("cq")) {
-      RegNo = Sparc::CPQ;
-      RegKind = SparcOperand::rk_Special;
-      return true;
+    // Canonicalize G0_G1 ... G30_G31 etc. to G0 ... G30.
+    if (MRI.getRegClass(SP::IntPairRegClassID).contains(Reg)) {
+      RegKind = SparcOperand::rk_IntReg;
+      return MRI.getSubReg(Reg, SP::sub_even);
     }
 
-    if (name.equals("wim")) {
-      RegNo = Sparc::WIM;
-      RegKind = SparcOperand::rk_Special;
-      return true;
+    // Canonicalize D0 ... D15 to F0 ... F30.
----------------
s-barannikov wrote:

Currently, we only accept %f0 - %f63 as valid register names. If an odd-numbered register is used in an instruction expecting a double-fp register, a diagnostic is issued:
```
test.s:1:17: error: invalid operand for instruction
faddd %f0, %f0, %f1
                ^
```
Similarly, for quad-fp registers:
```
test.s:1:17: error: invalid operand for instruction
faddq %f0, %f0, %f2
                ^
```
I can try to support %d and %q mnemonics, but I'd prefer to do this in a separate patch (this patch is supposed to be NFC).


https://github.com/llvm/llvm-project/pull/82165