[llvm] Initialize unsigned integer when declared (PR #81894)
Martin Wehking via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 19 05:36:48 PST 2024
https://github.com/MartinWehking updated https://github.com/llvm/llvm-project/pull/81894
>From 88d095fb4ad1f27e129d260ae7b00ac3cbcaf35c Mon Sep 17 00:00:00 2001
From: Martin <martin.wehking at codeplay.com>
Date: Thu, 15 Feb 2024 17:43:16 +0000
Subject: [PATCH 1/2] Initialize unsigned integer when declared
Initialize ModOpcode directly before the loop execution to silence
static analyzer warnings about the usage of an uninitialized variable.
This leads to a redundant assignment of ElV2F16 inside the first loop
execution, but also avoids superfluous emptiness checks of EltsV2F16
after the first execution of the loop.
---
.../AMDGPU/AMDGPUInstructionSelector.cpp | 36 ++++++++++---------
1 file changed, 19 insertions(+), 17 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 5657880279962b..4969e3e26612db 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -4075,28 +4075,30 @@ InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectWMMAModsF16NegAbs(MachineOperand &Root) const {
Register Src = Root.getReg();
unsigned Mods = SISrcMods::OP_SEL_1;
- unsigned ModOpcode;
SmallVector<Register, 8> EltsV2F16;
- if (GConcatVectors *CV = dyn_cast<GConcatVectors>(MRI->getVRegDef(Src))) {
- for (unsigned i = 0; i < CV->getNumSources(); ++i) {
- MachineInstr *ElV2F16 = MRI->getVRegDef(CV->getSourceReg(i));
+ if (GConcatVectors *CV = dyn_cast<GConcatVectors>(MRI->getVRegDef(Src)))
+ if (CV->getNumSources() > 0) {
+ MachineInstr *ElV2F16 = MRI->getVRegDef(CV->getSourceReg(0));
// Based on first element decide which mod we match, neg or abs
- if (EltsV2F16.empty())
- ModOpcode = (ElV2F16->getOpcode() == AMDGPU::G_FNEG) ? AMDGPU::G_FNEG
- : AMDGPU::G_FABS;
- if (ElV2F16->getOpcode() != ModOpcode)
- break;
- EltsV2F16.push_back(ElV2F16->getOperand(1).getReg());
- }
+ unsigned ModOpcode = (ElV2F16->getOpcode() == AMDGPU::G_FNEG)
+ ? AMDGPU::G_FNEG
+ : AMDGPU::G_FABS;
+
+ for (unsigned i = 0; i < CV->getNumSources(); ++i) {
+ ElV2F16 = MRI->getVRegDef(CV->getSourceReg(i));
+ if (ElV2F16->getOpcode() != ModOpcode)
+ break;
+ EltsV2F16.push_back(ElV2F16->getOperand(1).getReg());
+ }
- // All elements had ModOpcode modifier
- if (CV->getNumSources() == EltsV2F16.size()) {
- MachineIRBuilder B(*Root.getParent());
- selectWMMAModsNegAbs(ModOpcode, Mods, EltsV2F16, Src, Root.getParent(),
- *MRI);
+ // All elements had ModOpcode modifier
+ if (CV->getNumSources() == EltsV2F16.size()) {
+ MachineIRBuilder B(*Root.getParent());
+ selectWMMAModsNegAbs(ModOpcode, Mods, EltsV2F16, Src, Root.getParent(),
+ *MRI);
+ }
}
- }
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
[=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}};
>From e9c92efbabfffc7aa66e4b2b73692fb0b61da23e Mon Sep 17 00:00:00 2001
From: Martin Wehking <martin.wehking at codeplay.com>
Date: Mon, 19 Feb 2024 13:26:48 +0000
Subject: [PATCH 2/2] Extend unsigned integer initialization
Initialize ModOpcode directly similarly to
88d095fb4ad1f27e129d260ae7b00ac3cbcaf35c
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 9 ++--
.../AMDGPU/AMDGPUInstructionSelector.cpp | 53 ++++++++++---------
2 files changed, 32 insertions(+), 30 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 5278b552a65514..1f048abfb7584c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -3261,15 +3261,16 @@ bool AMDGPUDAGToDAGISel::SelectWMMAModsF32NegAbs(SDValue In, SDValue &Src,
SDValue &SrcMods) const {
Src = In;
unsigned Mods = SISrcMods::OP_SEL_1;
- unsigned ModOpcode;
SmallVector<SDValue, 8> EltsF32;
if (auto *BV = dyn_cast<BuildVectorSDNode>(stripBitcast(In))) {
+ assert(BV->getNumOperands() > 0);
+ // Based on first element decide which mod we match, neg or abs
+ SDValue ElF32 = stripBitcast(BV->getOperand(0));
+ unsigned ModOpcode =
+ (ElF32.getOpcode() == ISD::FNEG) ? ISD::FNEG : ISD::FABS;
for (unsigned i = 0; i < BV->getNumOperands(); ++i) {
SDValue ElF32 = stripBitcast(BV->getOperand(i));
- // Based on first element decide which mod we match, neg or abs
- if (EltsF32.empty())
- ModOpcode = (ElF32.getOpcode() == ISD::FNEG) ? ISD::FNEG : ISD::FABS;
if (ElF32.getOpcode() != ModOpcode)
break;
EltsF32.push_back(ElF32.getOperand(0));
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 4969e3e26612db..9e01c54da5c8b3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -4019,16 +4019,17 @@ InstructionSelector::ComplexRendererFns
AMDGPUInstructionSelector::selectWMMAModsF32NegAbs(MachineOperand &Root) const {
Register Src = Root.getReg();
unsigned Mods = SISrcMods::OP_SEL_1;
- unsigned ModOpcode;
SmallVector<Register, 8> EltsF32;
if (GBuildVector *BV = dyn_cast<GBuildVector>(MRI->getVRegDef(Src))) {
+ assert(BV->getNumSources() > 0);
+ // Based on first element decide which mod we match, neg or abs
+ MachineInstr *ElF32 = MRI->getVRegDef(BV->getSourceReg(0));
+ unsigned ModOpcode = (ElF32->getOpcode() == AMDGPU::G_FNEG)
+ ? AMDGPU::G_FNEG
+ : AMDGPU::G_FABS;
for (unsigned i = 0; i < BV->getNumSources(); ++i) {
- MachineInstr *ElF32 = MRI->getVRegDef(BV->getSourceReg(i));
- // Based on first element decide which mod we match, neg or abs
- if (EltsF32.empty())
- ModOpcode = (ElF32->getOpcode() == AMDGPU::G_FNEG) ? AMDGPU::G_FNEG
- : AMDGPU::G_FABS;
+ ElF32 = MRI->getVRegDef(BV->getSourceReg(i));
if (ElF32->getOpcode() != ModOpcode)
break;
EltsF32.push_back(ElF32->getOperand(1).getReg());
@@ -4077,29 +4078,29 @@ AMDGPUInstructionSelector::selectWMMAModsF16NegAbs(MachineOperand &Root) const {
unsigned Mods = SISrcMods::OP_SEL_1;
SmallVector<Register, 8> EltsV2F16;
- if (GConcatVectors *CV = dyn_cast<GConcatVectors>(MRI->getVRegDef(Src)))
- if (CV->getNumSources() > 0) {
- MachineInstr *ElV2F16 = MRI->getVRegDef(CV->getSourceReg(0));
- // Based on first element decide which mod we match, neg or abs
- unsigned ModOpcode = (ElV2F16->getOpcode() == AMDGPU::G_FNEG)
- ? AMDGPU::G_FNEG
- : AMDGPU::G_FABS;
-
- for (unsigned i = 0; i < CV->getNumSources(); ++i) {
- ElV2F16 = MRI->getVRegDef(CV->getSourceReg(i));
- if (ElV2F16->getOpcode() != ModOpcode)
- break;
- EltsV2F16.push_back(ElV2F16->getOperand(1).getReg());
- }
+ if (GConcatVectors *CV = dyn_cast<GConcatVectors>(MRI->getVRegDef(Src))) {
+ assert(CV->getNumSources() > 0);
+ MachineInstr *ElV2F16 = MRI->getVRegDef(CV->getSourceReg(0));
+ // Based on first element decide which mod we match, neg or abs
+ unsigned ModOpcode = (ElV2F16->getOpcode() == AMDGPU::G_FNEG)
+ ? AMDGPU::G_FNEG
+ : AMDGPU::G_FABS;
- // All elements had ModOpcode modifier
- if (CV->getNumSources() == EltsV2F16.size()) {
- MachineIRBuilder B(*Root.getParent());
- selectWMMAModsNegAbs(ModOpcode, Mods, EltsV2F16, Src, Root.getParent(),
- *MRI);
- }
+ for (unsigned i = 0; i < CV->getNumSources(); ++i) {
+ ElV2F16 = MRI->getVRegDef(CV->getSourceReg(i));
+ if (ElV2F16->getOpcode() != ModOpcode)
+ break;
+ EltsV2F16.push_back(ElV2F16->getOperand(1).getReg());
}
+ // All elements had ModOpcode modifier
+ if (CV->getNumSources() == EltsV2F16.size()) {
+ MachineIRBuilder B(*Root.getParent());
+ selectWMMAModsNegAbs(ModOpcode, Mods, EltsV2F16, Src, Root.getParent(),
+ *MRI);
+ }
+ }
+
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
[=](MachineInstrBuilder &MIB) { MIB.addImm(Mods); }}};
}
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