[llvm] [AArch64] Lowering of fpmode intrinsics in DAG (PR #80611)

[Serge Pavlov via llvm-commits]

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@@ -523,6 +523,9 @@ enum Rounding {
 // Bit position of rounding mode bits in FPCR.
 const unsigned RoundingBitsPos = 22;
 
+// Reserved bits should be preserved when modifying FPCR.
+const uint64_t ReservedFPControlBits = 0xfe0fe0f8;
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spavloff wrote:

You are right, thank you. The set of reserved bits was blindly copied from glibc: https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/aarch64/fpu/fpu_control.h;h=263cf36c057ae91bcf1175e39f392fc4caa84c10;hb=refs/heads/master#l49.

https://github.com/llvm/llvm-project/pull/80611