[llvm] [RISCV] Vector sub (zext, zext) -> sext (sub (zext, zext)) (PR #82455)

[Craig Topper via llvm-commits]

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@@ -12865,14 +12865,15 @@ static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
   //   where the sum of the extend widths match, and the inner zexts
   //   add at least one bit.  (For profitability on rvv, we use a
   //   power of two for both inner and outer extend.)
-  if (VT.isVector() && N0.getOpcode() == N1.getOpcode() && N0.hasOneUse() &&
-      N1.hasOneUse() && N0.getOpcode() == ISD::ZERO_EXTEND) {
+  if (VT.isVector() && Subtarget.getTargetLowering()->isTypeLegal(VT) &&
+      N0.getOpcode() == N1.getOpcode() && N0.hasOneUse() && N1.hasOneUse() &&
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topperc wrote:

Check the opcode before checking the use count. hasOneUse is expensive for nodes that produce multiple results. It can't stop at the second use. It has to check all uses of all results. This is can get especially bad with the chain output of loads. So we've found that is best to make sure the opcode is one that only produces one result first.

https://github.com/llvm/llvm-project/pull/82455