[llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)

[Brendan Sweeney via llvm-commits]

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@@ -105,22 +105,66 @@ defm AMOMAXU_D  : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">,
 // Pseudo-instructions and codegen patterns
 //===----------------------------------------------------------------------===//
 
+// An atomic load operation that does not need either acquire or release
+// semantics.
+class relaxed_load<PatFrags base>
+  : PatFrag<(ops node:$ptr), (base node:$ptr)> {
+  let IsAtomic = 1;
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mehnadnerd wrote:

I did it this way to match the AArch64 lowerings (llvm/lib/Target/AArch64/AArch64InstrAtomics.td), which this is adapted from.

https://github.com/llvm/llvm-project/pull/82914