[llvm] [RISCV] Use PromoteSetCCOperands to promote operands for UMAX/UMIN during type legalization. (PR #82716)

[David Sherwood via llvm-commits]

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@@ -1343,10 +1343,14 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
+  SDValue LHS = N->getOperand(0);
+  SDValue RHS = N->getOperand(1);
+
   // It doesn't matter if we sign extend or zero extend in the inputs. So do
-  // whatever is best for the target.
-  SDValue LHS = SExtOrZExtPromotedInteger(N->getOperand(0));
-  SDValue RHS = SExtOrZExtPromotedInteger(N->getOperand(1));
+  // whatever is best for the target and the promoted operands. We can reuse
+  // PromoteSetCCOperands by passing it an unsigned predicate.
+  PromoteSetCCOperands(LHS, RHS, ISD::SETUGT);
----------------
david-arm wrote:

I guess here you're making the assumption that whatever operation is used for umin/umax that the promotion operation will be the same. In theory I can imagine umin/umax using any one of ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE. In practice, do you think the promotion behaviour will be different between those 4?

https://github.com/llvm/llvm-project/pull/82716