[llvm] [CodeGenSchedule] Don't allow invalid ReadAdvances to be formed (PR #82685)

[Visoiu Mistrih Francis via llvm-commits]

francisvm wrote:

@ebahapo both the ExynosM4 and ExynosM5 models have a `M5WriteFMAC5` that is not associated with any instruction. Are you missing an `InstRW` somewhere, or can we get rid of it from the list of `ValidWrites`?

```
def M4WriteFMAC5   : SchedWriteRes<[M4UnitFMAC]>  { let Latency = 5; }
def M4ReadFMACM1   : SchedReadAdvance<+1, [M4WriteFMAC4,
                                           M4WriteFMAC4H,
                                           M4WriteFMAC5]>;
// no other references of M4WriteFMAC5
```

https://github.com/llvm/llvm-project/pull/82685