[llvm] [HEXAGON] Fix bit boundary for isub_hi in HexagonBitSimplify (PR #82336)

[via llvm-commits]

https://github.com/yandalur updated https://github.com/llvm/llvm-project/pull/82336

>From 6278f7fb77ad7802c4790b0a041b41c3d21f5a55 Mon Sep 17 00:00:00 2001
From: Yashas Andaluri <quic_yandalur at quicinc.com>
Date: Tue, 20 Feb 2024 15:41:01 +0530
Subject: [PATCH] [HEXAGON] Fix bit boundary for isub_hi in HexagonBitSimplify

Use bit boundary of 32 for high subregisters in HexagonBitSimplify.
This fixes the subregister used in an upper half register store.
---
 .../lib/Target/Hexagon/HexagonBitSimplify.cpp |  3 ++-
 .../Hexagon/bit-store-upper-sub-hi.mir        | 21 +++++++++++++++++++
 2 files changed, 23 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/Hexagon/bit-store-upper-sub-hi.mir

diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 6024d9f7b1547c..3b8234c0118435 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1957,7 +1957,8 @@ bool BitSimplification::genStoreUpperHalf(MachineInstr *MI) {
     return false;
   const BitTracker::RegisterCell &RC = BT.lookup(RS.Reg);
   RegHalf H;
-  if (!matchHalf(0, RC, 0, H))
+  unsigned B = (RS.Sub == Hexagon::isub_hi) ? 32 : 0;
+  if (!matchHalf(0, RC, B, H))
     return false;
   if (H.Low)
     return false;
diff --git a/llvm/test/CodeGen/Hexagon/bit-store-upper-sub-hi.mir b/llvm/test/CodeGen/Hexagon/bit-store-upper-sub-hi.mir
new file mode 100644
index 00000000000000..ef84043cf50212
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/bit-store-upper-sub-hi.mir
@@ -0,0 +1,21 @@
+# RUN: llc -march=hexagon -run-pass=hexagon-bit-simplify -o - %s | FileCheck %s
+
+# This test checks if the HexagonBitSimplify pass correctly replaces a
+# S2_storerh_io with a S2_storerf_io that stores the upper halfword
+# of a high subregister using appropriate subregister boundaries.
+
+# CHECK: S2_storerf_io %0, 28, %{{[0-9]+}}.isub_hi
+# CHECK-NOT: S2_storerf_io %0, 28, %{{[0-9]+}}.isub_lo
+
+---
+name: test_store
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $r0
+    %0:intregs = COPY $r0
+    %1:doubleregs = IMPLICIT_DEF
+    %2:doubleregs = IMPLICIT_DEF
+    %3:doubleregs = S2_shuffoh %2, %1
+    S2_storerh_io %0, 28, %3.isub_hi
+...