[llvm] 2426055 - [RISCV] Add more zext nneg tests. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-02-19T11:09:43-08:00
New Revision: 2426055a64e43c5d9126b191ee9836710a223d75

URL: https://github.com/llvm/llvm-project/commit/2426055a64e43c5d9126b191ee9836710a223d75
DIFF: https://github.com/llvm/llvm-project/commit/2426055a64e43c5d9126b191ee9836710a223d75.diff

LOG: [RISCV] Add more zext nneg tests. NFC

This adds additional tests for #82199.

These tests need us to propagate the nneg flag when we zero/sign
extend an existing zext nneg node. For these tests on RV64, call
lowering will need to sign extend or zero extend the existing zext
nneg to i64. getNode will fold this into a single zext. We should
propagate the nneg flag from the original zext nneg. This will allow
us to remove the zext nneg based on known sign bits during DAG combine.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/sext-zext-trunc.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
index af136806f71845..1257e7ee3df9dc 100644
--- a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
+++ b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
@@ -822,3 +822,85 @@ define void @zext_nneg_dominating_icmp_i32(i16 signext %0) {
 }
 
 declare void @bar_i32(i32)
+
+; Test that we propage zext nneg when we sign extend it on RV64 for the call to
+; bar_i32.
+define void @zext_nneg_dominating_icmp_i32_signext(i16 signext %0) {
+; RV32I-LABEL: zext_nneg_dominating_icmp_i32_signext:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    bltz a0, .LBB48_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    tail bar_i32
+; RV32I-NEXT:  .LBB48_2:
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: zext_nneg_dominating_icmp_i32_signext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    bltz a0, .LBB48_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    slli a0, a0, 48
+; RV64I-NEXT:    srli a0, a0, 48
+; RV64I-NEXT:    tail bar_i32
+; RV64I-NEXT:  .LBB48_2:
+; RV64I-NEXT:    ret
+;
+; RV64ZBB-LABEL: zext_nneg_dominating_icmp_i32_signext:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    bltz a0, .LBB48_2
+; RV64ZBB-NEXT:  # %bb.1:
+; RV64ZBB-NEXT:    zext.h a0, a0
+; RV64ZBB-NEXT:    tail bar_i32
+; RV64ZBB-NEXT:  .LBB48_2:
+; RV64ZBB-NEXT:    ret
+  %2 = icmp sgt i16 %0, -1
+  br i1 %2, label %3, label %5
+
+3:
+  %4 = zext nneg i16 %0 to i32
+  tail call void @bar_i32(i32 signext %4)
+  br label %5
+
+5:
+  ret void
+}
+
+; Test that we propage zext nneg when we zero extend it on RV64 for the call to
+; bar_i32.
+define void @zext_nneg_dominating_icmp_i32_zeroext(i16 signext %0) {
+; RV32I-LABEL: zext_nneg_dominating_icmp_i32_zeroext:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    bltz a0, .LBB49_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    tail bar_i32
+; RV32I-NEXT:  .LBB49_2:
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: zext_nneg_dominating_icmp_i32_zeroext:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    bltz a0, .LBB49_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    slli a0, a0, 48
+; RV64I-NEXT:    srli a0, a0, 48
+; RV64I-NEXT:    tail bar_i32
+; RV64I-NEXT:  .LBB49_2:
+; RV64I-NEXT:    ret
+;
+; RV64ZBB-LABEL: zext_nneg_dominating_icmp_i32_zeroext:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    bltz a0, .LBB49_2
+; RV64ZBB-NEXT:  # %bb.1:
+; RV64ZBB-NEXT:    zext.h a0, a0
+; RV64ZBB-NEXT:    tail bar_i32
+; RV64ZBB-NEXT:  .LBB49_2:
+; RV64ZBB-NEXT:    ret
+  %2 = icmp sgt i16 %0, -1
+  br i1 %2, label %3, label %5
+
+3:
+  %4 = zext nneg i16 %0 to i32
+  tail call void @bar_i32(i32 signext %4)
+  br label %5
+
+5:
+  ret void
+}