[llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)

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git-clang-format --diff a8c3b3e20db01d2947dbe87d0c557150ed777865 0e3ec6ab9873a8cccee2e39919186395eddeffc9 -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVISelLowering.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d1829903a0..b6bd6097e8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20842,9 +20842,12 @@ bool RISCVTargetLowering::shouldInsertFencesForAtomic(
       //  will just not insert any fences
       auto LI = dyn_cast<LoadInst>(I);
       auto SI = dyn_cast<StoreInst>(I);
-      if ((LI && (LI->getOrdering() == AtomicOrdering::SequentiallyConsistent))
-       || (SI && (SI->getOrdering() == AtomicOrdering::SequentiallyConsistent))) {
-        // Here, this is a load or store which is seq_cst, and needs a .aq or .rl
+      if ((LI &&
+           (LI->getOrdering() == AtomicOrdering::SequentiallyConsistent)) ||
+          (SI &&
+           (SI->getOrdering() == AtomicOrdering::SequentiallyConsistent))) {
+        // Here, this is a load or store which is seq_cst, and needs a .aq or
+        // .rl
         //  therefore we shouldn't try to insert fences
         return false;
       }

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https://github.com/llvm/llvm-project/pull/82914