[llvm] [RISCV] Fix mgather -> riscv.masked.strided.load combine not extending indices (PR #82506)

[Luke Lau via llvm-commits]

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@@ -15086,22 +15086,18 @@ define <32 x i64> @mgather_strided_split(ptr %base) {
   ret <32 x i64> %x
 }
 
-; FIXME: This is a miscompile triggered by the mgather ->
-; riscv.masked.strided.load combine. In order for it to trigger we need either a
-; strided gather that RISCVGatherScatterLowering doesn't pick up, or a new
-; strided gather generated by the widening sew combine.
 define <4 x i32> @masked_gather_widen_sew_negative_stride(ptr %base) {
 ; RV32V-LABEL: masked_gather_widen_sew_negative_stride:
 ; RV32V:       # %bb.0:
-; RV32V-NEXT:    addi a0, a0, -128
+; RV32V-NEXT:    addi a0, a0, 128
 ; RV32V-NEXT:    li a1, -128
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lukel97 wrote:

I've updated the test in 11d115d0569b212dfeb7fe6485be48070e068e19 to make the stride larger than 128

https://github.com/llvm/llvm-project/pull/82506