[llvm] [RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (PR #82914)

[Brendan Sweeney via llvm-commits]

================
@@ -5,13 +5,20 @@
 ; RUN:   | FileCheck -check-prefixes=RV32IA,RV32IA-WMO %s
 ; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefixes=RV32IA,RV32IA-TSO %s
+; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-zalasr -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefixes=RV32IA,RV32IA-ZALASR,RV32IA-ZALASR-WMO %s
+; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-zalasr,+experimental-ztso -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefixes=RV32IA,RV32IA-ZALASR,RV32IA-ZALASR-TSO %s
----------------
mehnadnerd wrote:

There is a difference between ZALASR-TSO and TSO: the lowering of seq_cst loads and stores differs between them.
Between ZALASR-TSO and ZALASR-WMO, they differ in the lowering of acq loads and rel stores.
Since the RV32IA-ZALASR prefix takes precedence when they match, for seq_cst loads/stores they are listed as RV32AA-ZALASR loads/stores.

https://github.com/llvm/llvm-project/pull/82914